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Compare 12 IP from 6 vendors (1 - 10)
  • 100G OTN Regenerator/Repeater(OTL4.4)
    • 200MHz+ push button core performance.
    • All products designed from ground up to allow future datapath & channel scaling.
    • Softcore Microprocessor subsystem connected to generic core registers.
    • OTL4.4 client & line interface.
  • Multi-LEO Satellite Link Emulator
    • Multi-LEO Simulation
    • Dynamic Channel Modelling
    • Flexible Configuration
    • Scalability
  • NTN eNodeB System Test Bench
    • Allows end-to-end testing of NB-IoT NTN system in lab environment.
    • supports 3GPP® Release 17 and 18 standards.
    • supports LEO transparent or regenerative modes of operation.
    • multiple-instancing and virtualisation to simulate UE community.
    Block Diagram -- NTN eNodeB System Test Bench
  • NTN System Test Bench
    • Allows end-to-end testing of NB-IoT NTN system in lab environment.
    • supports 3GPP® Release 17 and 18 standards.
    • supports LEO transparent or regenerative modes of operation.
    • multiple-instancing and virtualisation to simulate UE community.
    Block Diagram -- NTN System Test Bench
  • Low-power high-speed reconfigurable processor to accelerate AI everywhere.
    • Multi-Core Number: 4
    • Performance (INT8, 600MHz): 0.6TOPS
    • Achievable Clock Speed (MHz): 600 (28nm)
    • Synthesis Logic Gates (MGates): 2
    Block Diagram -- Low-power high-speed reconfigurable processor to accelerate AI everywhere.
  • Media Access Control Security (MACSec)
    • Up to four ports of concurrent traffic with an aggregate bandwidth of 100G are supported by one core (1x100G, 2x50G, 2x40G, 4x25G, 4x10G, 4x1G, 1x50G+2x25G)
    • Line rate operation
    • Flexible control/non-control port filtering
    • Configurable number of Secure Channels (SCs) and Security Associations (SAs) per physical port
    Block Diagram -- Media Access Control Security (MACSec)
  • eDP 1.4 Receiver
    • Compliant with Embedded DisplayPort 1.4 specification
    • Support for up to 4 Dual-Speed lanes at 1.62 Gbit/s and 2.7 Gbit/s
    • Supports Enhanced Framing Mode
    • Integrated High-bandwidth Digital Content Protection (HDCP) version 1.4
    Block Diagram -- eDP 1.4 Receiver
  • DisplayPort 1.2 Receiver
    • Compliant with DisplayPort Standard 1.2
    • Main Link supports 1, 2 or 4 lanes at 1.62Gbps, 2.7Gbps and 5.4Gbps
    • Enhanced Framing Mode support
    • Integrated High-bandwidth Digital Content Protection (HDCP) version 1.4
    Block Diagram -- DisplayPort 1.2 Receiver
  • HDMI 2.0 Receiver with MHL 2.0
    • HDMI 2.0 Specification, MHL 2.0 Specification and HDCP 1.4 Specification compliant
    Block Diagram -- HDMI 2.0 Receiver with MHL 2.0
  • ATSC Remultiplexer N-to-M
    • Supported FPGA families: Xilinx Spartan-6, Virtex-6, Artix-7, Kintex-7, Virtex-7, Zynq
    • N SPI input / M SPI output (N and M from 1 to 8)
    • Adapt one or several MPTS/SPTS stream rate into one or several MPTS by filtering and multiplexing complete services
    • Management of PSIP tables (automatic tables generator) according to ATSC A/65:2009, A/53:part 3 and ISO 13818-1.
    Block Diagram -- ATSC Remultiplexer N-to-M
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