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RISC-V Vector CPU IP

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Compare 24 IP from 11 vendors (1 - 10)
  • Multi-core capable 64-bit RISC-V CPU with vector extensions
    • The SiFive® Intelligence™ X180 core IP products are designed to meet the increasing requirements of embedded IoT and AI at the far edge.
    • With this 64-bit version, X100 series IP delivers higher performance and better integration with larger memory systems.
    Block Diagram -- Multi-core capable 64-bit RISC-V CPU with vector extensions
  • Multi-core capable 32-bit RISC-V CPU with vector extensions
    • The SiFive® Intelligence™ X160 core IP products are designed to meet the increasing requirements of embedded IoT and AI at the far edge.
    • With this 32-bit version, X100 series IP can be optimized for power efficiency and severely area-constrained applications.
    Block Diagram -- Multi-core capable 32-bit RISC-V CPU with vector extensions
  • 64-bit CPU with RISC-V Vector Extension
    • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
    • RISC-V vector extension
    • Vector Processing Unit (VPU) boost the performance of AI, AR/VR, computer vision, cryptography, and multimedia processing
    • Andes extensions, architected for performance and functionality enhancements
    Block Diagram -- 64-bit CPU with RISC-V Vector Extension
  • RISC-V CPU IP
    • RISC-V RVA23 Compliant 
    • >18 SPECint2006/GHz
    • 8-wide decode unit
    • Advanced branch predictor
    Block Diagram -- RISC-V CPU IP
  • High-performance RISC-V CPU
    • Fully compliant with the RVA23 RISC-V specification
    • Comparable PPA to Arm Neoverse V3 / Cortex-X4
    • Standard AMBA CHI.E coherent interface for SoC and chiplet integration
    • Co-architected with Veyron E2 for seamless vector, AI acceleration, and big-little style heterogeneous compute configurations
    Block Diagram -- High-performance RISC-V CPU
  • 64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
    • 64-bit in-order dual-issue 8-stage CPU core with up to 1024-bit Vector Processing Unit (VPU)
    • Symmetric multiprocessing up to 8 cores
    Block Diagram -- 64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
  • Vector-Capable Embedded RISC-V Processor
    • The EMSA5-GP is a highly-featured 32-bit RISC-V embedded processor IP core optimized for processing-demanding applications.
    • It is equipped with floating-point and vector-processing units, cache memories, and is suitable for concurrent execution in a multi-processor environment.
    Block Diagram -- Vector-Capable Embedded RISC-V Processor
  • 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
    • 2 different packages with or without vector: AX46MPV, AX46MP
    • in-order dual-issue 8-stage CPU core with up to 2048-bit VLEN
    • Symmetric multiprocessing up to 16 cores
    • Private Level-2 cache
    • Shared L3 cache and coherence support
    Block Diagram -- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
  • 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
    • AndesCore™ A46MP(V) 32-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeStar™ V5 architecture and Andes Matrix Multiply (AMM) extension.
    • It supports RISC-V standard “G (IMA-FD)”, “ZC” compression, “B” bit manipulation, DSP/SIMD ‘P’ (draft), “V” (vector), CMO (cache management) extensions, Andes performance enhancements, plus Andes Custom Extension™ (ACE) for user-defined instructions.
    Block Diagram -- 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
  • All-In-One RISC-V NPU
    • Optimized Neural Processing for Next-Generation Machine Learning with High-Efficiency and Scalable AI compute
    Block Diagram -- All-In-One RISC-V NPU
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