RISC-V CPU IP

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Compare 73 IP from 25 vendors (1 - 10)

RISC-V CPU IP
- RISC-V RVA23 Compliant
- >18 SPECint2006/GHz
- 8-wide decode unit
- Advanced branch predictor
32-bit RISC-V CPU with M, Zicsr extensions, and External Debug support
- Five-stage pipeline
- Harvard architecture
- RV32I Base RISC-V ISA
64-bit RISC-V CPU with M, Zicsr extensions and External Debug support
- Five-stage pipeline
- Harvard architecture
- RV64I Base RISC-V ISA
Low Power RISCV CPU
- RISC-V RV32 instruction set:
- Machine mode only
- 32 vectorized interrupts
- Standard debug as defined per RISC-V
RISC-V CPU IP With ISO 26262 Full Compliance
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extensions
- Bit-manipulation extensions
Ultra Compact 32-bit RISC-V CPU Core
- AndeStar™ V5/V5e Instruction Set Architecture (ISA)
- Compliant to RISC-V technology
- Support RV32IMAC/EMAC
RISC-V Processor - RV12 - 32/64 bit, Single Core CPU
- High Performance 32/64bit CPU
- Highly Parameterized
- Size and power optimized design
- Industry standard software support
Ultra-low power RISC-V microcontroller CPU
- High efficient instruction execution pipeline
- Ultra-low power, high energy efficiency
- flexible custom instructions
Data Movement Engine - Best in class multi-core high-performance AI-enabled RISC-V Automotive CPU for ADAS, AVs and SDVs
- The only Multi-Threaded Out-of-Order RISC-V Core with ASIL-B Certification
- Highly scalable multi-core, multi-cluster, coherent computing solution
- MIPS extensions for improved performance and functionality
- Use in Automotive, Datacenter, and Embedded applications
64-bit CPU with RISC-V Vector Extension
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- RISC-V vector extension