RAM RHEA compiler IP
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Highly-optimized PQC implementations, capable of running PQC in under 15kb RAM
- PQCryptoLib-Emebedded is a versatile, CAVP-ready cryptography library designed and optimized for embedded devices.
- With its design focused on ultra-small memory footprint, PQCryptoLib-Embedded solutions have been specically designed for embedded systems, microcontrollers and memory-constrained devices. It provides a PQC integration to devices already in the field.
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High performance 8-bit micro-controller with 256 bytes on-chip Data RAM, three 16-bit timer/counters, and two 16-bit dptr; 0.25um UMC Logic process.
- 8-bit CPU pin and instruction set compatible with 8032
- Additional DEC DPTR instruction
- 64K external program memory
- 64K external data memory
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Register Indirect RAM Access
- Easy integraton
- AMBA AHB 3.0 Compatible
- AHB Reads, Writes
- Burst Types: Single, INCR, INCR4, INCR18, INCR16
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USB 2.0 Device, Software based enumeration RAM Interface (USB20SR)
- USB 2.0 USB IF high-speed certified (TID# 70680007)
- Supports both High Speed (480 Mbps) and Full Speed (12 Mbps)
- High speed or Full speed operation selection through Software
- ULPI Interface support
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RAM 8b, 16b, and 32b data widths - TSMC 180nm
- 8b, 16b, and 32b data widths available.
- Up to 250MHz clock operation.
- Read and write data busses may tie for single bus operation.
- Available production test RTL.
- VDD 1.6V – 2.0V.
- Data retention to 0.9V.
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Static RAM Controller
- The SRAM-CTRL implements a Static Random Access Memory (SRAM) Controller translating AHB, or AXI4, or APB bus reads and writes into reads and writes with the signaling and timing of a standard 32-bit synchronous SRAM.
- The type of host interface is user-defined at synthesis time.
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DMA Unit
- The DMU signals to the attached DMA Controller (DMA request) when there is a newly received message available at one of the attached M_CAN's Rx FIFOs respectively when there is the possibility to load a new Tx message into the M_CAN's Tx FIFO/Queue.
- The DMA controller then autonomously transfers the received message from the M_CAN's Message RAM to the System Memory or the message to be transmitted from the System Memory to the M_CAN's Message RAM.
