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PCIe Gen3 IP

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Compare 64 IP from 23 vendors (1 - 10)
  • PCIe Gen3 Class SSCG PLL on TSMC CLN16FFC
    • High performance design emphasis for meeting low jitter requirements in PCI Express applications
    • Implemented with Analog Bits’ proprietary architecture
    • Low power consumption
    • Spread Spectrum Clock Generation (SSCG) and tracking capability
  • PCIe Gen3 Class SSCG PLL on TSMC CLN12FFC
    • High performance design emphasis for meeting low jitter requirements in PCI Express applications
    • Implemented with Analog Bits’ proprietary architecture
    • Low power consumption
    • Spread Spectrum Clock Generation (SSCG) and tracking capability
  • PCIe Gen3 Class SSCG PLL on GLOBALFOUNDRIES 12LP+
    • High performance design emphasis for meeting low jitter requirements in PCI Express applications
    • Implemented with Analog Bits’ proprietary architecture
    • Low power consumption
    • Spread Spectrum Clock Generation (SSCG) and tracking capability
  • PCIe Gen3 Class SSCG PLL on GLOBALFOUNDRIES 12LP
    • High performance design emphasis for meeting low jitter requirements in PCI Express applications
    • Implemented with Analog Bits’ proprietary architecture
    • Low power consumption
    • Spread Spectrum Clock Generation (SSCG) and tracking capability
  • Low Power PCIe Gen3 PHY on TSMC CLN16FFC
    • Industry leading low power PMA macro – 36mW per lane at 8Gbps (4.5mW/Gbps), inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.133 mm2 total active area per lane
    • Supported protocols include: PCIe Gen3/2/1, SATA3/2/1, XAUI/RXAUI, SGMII
    • Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and 5- tap DFE
  • Low Power PCIe Gen3 PHY on TSMC CLN12FFC
    • Industry leading low power PMA macro – 39mW per lane at 8Gbps (4.88mW/Gbps), inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.133 mm2 total active area per lane
    • Supported protocols include: PCIe Gen3/2/1, SATA3/2/1, XAUI/RXAUI, SGMII
    • Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and 5- tap DFE
  • PCIe Gen3 PHY
    • Low Risk - Silicon proven with Si characterization data
    • Excellent Interoperability
    • Superior Noise Immunity
    Block Diagram -- PCIe Gen3 PHY
  • AXI Bridge for PCI Express (PCIe) Gen3 Subsystem
    • Maximum Payload Size (MPS) up to 256 Bytes
    • Messaged Signaled Interrupt (MSI)
    • Memory mapped AXI4 access to PCIe space
    • PCIe access to memory mapped AXI4 space
  • PCIe 3.0 (Gen3) Standard Controller with AMBA bridge II
    • Supports all required features of the PCI Express 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1 (5 GT/s), 1.1 (2.5 GT/s) and PIPE (8-, 16- and 32-bit) specifications
    • Production-proven datapath support for 32b, 64b, 128b, 256b and 512b implementations
    • Fully compliant with the PCI-SIG Single-Root I/O Virtualization (SRIOV) specification
    • Application interfaces include the Synopsys native interface or the optional ARM® AMBA® 4 AXI and 3 AXI application interface (AMBA not available for Switch configurations)
    Block Diagram -- PCIe 3.0 (Gen3) Standard Controller with AMBA bridge II
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