PCIe 3 PHY IP
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99
IP
from 11 vendors
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10)
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Low Power PCIe Gen3 PHY on TSMC CLN16FFC
- Industry leading low power PMA macro – 36mW per lane at 8Gbps (4.5mW/Gbps), inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.133 mm2 total active area per lane
- Supported protocols include: PCIe Gen3/2/1, SATA3/2/1, XAUI/RXAUI, SGMII
- Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and 5- tap DFE
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Low Power PCIe Gen3 PHY on TSMC CLN12FFC
- Industry leading low power PMA macro – 39mW per lane at 8Gbps (4.88mW/Gbps), inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.133 mm2 total active area per lane
- Supported protocols include: PCIe Gen3/2/1, SATA3/2/1, XAUI/RXAUI, SGMII
- Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and 5- tap DFE
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PHY for PCIe 3.1
- Supports PCIe 3.1, USB 3.1, DP-TX v1.4/eDP-TX v1.4b, SATA 3, 10G-KR and QSMII/SGMII
- Multi-protocol support for simultaneous independent links
- Supports SRIS and internal SSC generation
- Supports PCIe L1 sub-states
- Automatic calibration of on-chip termination resistors
- Supports internal and external clock sources with clock active detection
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10Gbps Multi-Link and Multi-Protocol PCIe 4.0 PHY IP for SMIC
- Supports USB 3.1, PCIe 3.0/2.0/1.0, DP-TX v1.4/ eDP-TX v1.4b, SATA 3, QSGMII,and SGMII
- Supports PCIe L1 sub-states
- Supports SRIS and internal SSC generation
- Multi-protocol support for simultaneous independent links
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10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
- Supports USB 3.1, PCIe 3.0/2.0/1.0, DP-TX v1.4/ eDP-TX v1.4b, SATA 3, 10G-KR and SGMII
- Supports PCIe L1 sub-states
- Supports SRIS and internal SSC generation
- Supports internal and external clock sources with clock active detection
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PCIe 3.0 Serdes PHY IP, Silicon Proven in GF 22FDX
- Silicon Proven in GF 22GDX with 0.8V and 1.8V power supply.
- Compatible with PCIe base Specification
- Support 32-bit/16-bit parallel interface
- Support for PCIe3(8.0Gbps)
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PCIe Express Gen4 / Ethernet SERDES on TSMC CLN5A
- Industry leading low power PMA macro – 122.9mW per lane at 16Gbps (7.7mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
- Support for Ethernet protocols and Automotive Grade 2
- Compact form factor – 0.34 mm2 active silicon area per lane including ESD
- Minimal latency – 3 UI between parallel transfer and serial transmission
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PCI Express Gen5 SERDES PHY on Samsung 8LPP
- Industry leading low power PMA macro – 224mW per lane at 28Gbps (8.0 mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.38 mm2 active silicon area per lane including ESD
- Minimal latency – 3 UI between parallel transfer and serial transmission
- Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
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PCI Express Gen4 SERDES PHY on Samsung 7LPP
- Industry leading low power PMA macro – 132.7mW per lane at 16Gbps (8.4mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.32 mm2 active silicon area per lane including ESD
- Minimal latency – 3 UI between parallel transfer and serial transmission
- Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
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PCI Express Gen3/Enterprise Class SERDES PHY on Samsung 28LPP
- Industry leading low power PMA macro – 88mW per lane at 8Gbps (11.0 mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.216 mm2 active silicon area per lane including ESD
- Enterprise class Long Reach 5-tap DFE supporting beyond standard PCIe Channels
- Minimal latency – 3 UI between parallel transfer and serial transmission