IP Catalog > Interface IP > Interconnect IP > Serdes IP > PCI Express Gen5 SERDES PHY on Samsung 8LPP

PCI Express Gen5 SERDES PHY on Samsung 8LPP

Overview

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY for PCIe 5.0 operates at 2.5Gbps, 5Gbps, 8Gbps, 16Gbps and 32Gbps, and is designed to meet higher performance standards required for enterprise market applications. The PHY additionally features an interface capability that allows integration with other customer-designed serial protocol PCS layers at any baud rate up to 16Gbps.

The PMA is delivered as a hard macro while the fully-synthesizable soft PCS includes performing all necessary calibration and self-test functions. The universal PHY architecture allows forming arbitrarily wide efficient links by being independent of the need for a common CMU.

Key Features

  • Industry leading low power PMA macro – 224mW per lane at 28Gbps (8.0 mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
  • Compact form factor – 0.38 mm2 active silicon area per lane including ESD
  • Minimal latency – 3 UI between parallel transfer and serial transmission
  • Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
  • Multi-orientation macros of 4, 8 and 16 lane SERDES are available for most common metal stacks
  • Exhibits exceptional input sensitivity, input jitter tolerance and low output jitter
  • Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and DFE
  • Finely configurable driver impedance, amplitude and 3-tap FFE
  • Supports multiple low-power modes
  • Test support features such as near-end loopback, reverse loopback, PRBS generator+checker, PLL bypass modes, etc.
  • Includes PIPE Compliant PCIe PCS with programmable PIPE frequencies, and supporting bifurcation, lane/link powerdown, SRNS, SRIS and L1-substates
  • Supports industry standard third-party controllers for PCIe
  • Low pin-count and suitable for a variety of flip-chip packages when paired with onchip T-coils
  • Metallization scheme and pad/bump structures customizable to specifications

Technical Specifications

Foundry, Node
Samsung 8LPP
Samsung
Pre-Silicon: 8nm
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