ONFI 4.0 Flash Memory IP
Filter
Compare
2
IP
from
2
vendors
(1
-
2)
-
Simulation VIP for ONFi
- Hundreds of protocol and timing checkers to easily catch design bugs
- Hundreds of predefined configurations based on specific memory vendors' part numbers, datasheets, or generic JEDEC definitions available on ememory.com(opens in a new tab)
- Transaction and memory callbacks for all protocol, model states and device memory events
-
Advanced Flash Controller Interface Core
- Multi-Port Architecture allows connecting up to 32 NAND devices (128 total NAND targets)
- Separate Administrative and I/O queues for flexible datapath management
- Maximum of 1 register write per command submission/ completion
- Industry standard bus interface (AXI-4) master used for command fetching, command completion, and data movement