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ONFI 3.2 NAND Controller IP

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  • ONFI 3.2 NAND Flash Controller IP Compliant to JEDEC
    • Compliant to ONFI 3.2 Specification
    • Supports SDR, NV-DDR and NV-DDR2
    • Included synthesizable PLL/DLL
    • ONFI 3.2 compatible 1.8v NV-DDR2 I/O pads supporting up to 533MT/s is available
    Block Diagram -- ONFI 3.2 NAND Flash Controller IP Compliant to JEDEC
  • ONFI 3.2 NAND Flash PHY IP Compliant to JEDEC
    • Compliant to ONFI revision 3.2 standard
    • Silicon proven PLL to support all frequencies from 10MHz to 266MHz, and DLL to improve data sampling accuracy dynamically
    • Include ONFI 3.2 I/O pads compatible to 1.8v NV-DDR2 533 MT/s and 3v NV-DDR 200 MT/s
    • Supports NV-DDR2 mode of operation supporting up to 266MHz
    Block Diagram -- ONFI 3.2 NAND Flash PHY IP Compliant to JEDEC
  • ONFI Nand Flash Software Driver
    • Compliant with ONFI 3.2 and backward compatible to ONFI 3.0, 2.3 and 1.0
    • Supports SDR, NV-DDR and NV-DDR2, Toggle DDR/DDR2 modes
    • Easy-to-use interface for applications
    • Support up to NAND with 16K page size
    Block Diagram -- ONFI Nand Flash Software Driver
  • Advanced Flash Controller Interface Core
    • Multi-Port Architecture allows connecting up to 32 NAND devices (128 total NAND targets)
    • Separate Administrative and I/O queues for flexible datapath management
    • Maximum of 1 register write per command submission/ completion
    • Industry standard bus interface (AXI-4) master used for command fetching, command completion, and data movement
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