Mixel IP
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108
IP
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10)
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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI C-PHY/D-PHY Combo RX+ IP 4.5Gsps/4.5Gbps in TSMC N5
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI C-PHY/D-PHY Combo TX+ IP 4.5Gsps/4.5Gbps in TSMC N5
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP in TSMC 40ULP
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 1 Data lanes in D-PHY mode
- Consists of 1 Data Trio in C-PHY mode
- Supports both low-power mode and high-speed mode with integrated SERDES
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MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 4.5Gsps/4.5Gbps
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.1
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
- Consists of 3 Data lanes in C-PHY mode
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MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 22ULL
- Supports MIPI Alliance Specification for D-PHY Version 2.5
- Consists of 1 Clock lane and 4 Data lanes
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MIPI D-PHY CSI-2 RX+ (Receiver) IP in TSMC 28HPM
- Consists of 1 Clock lane and 2 Data lanes
- Complies with MIPI Standard 1.1 for D-PHY
- Supports both high speed and lowpower modes
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MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.1 & C-PHY v1.2
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
- Consists of 3 Data lanes in C-PHY mode
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MIPI D-PHY CSI-2 RX+ IP in TSMC 28HPC+ for Automotive Applications
- Supports MIPI Alliance Specification for D-PHY Version 2.5
- Consists of 1 Clock lane and 2 Data lanes
- Embedded, high performance, and highly programmable PLL
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MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.1 & C-PHY v1.2
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
