Memory Subsystem IP
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157
IP
from 39 vendors
(1
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10)
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Universal NVM Express Controller (UNEX)
- Compliant to NVM Express 1.1
- Support for configurable number of IO Queues
- Support for configurable Queue depth
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Highly scalable inference NPU IP for next-gen AI applications
- Matrix Multiplication: 4096 MACs/cycles (int 8), 1024 MACs/cycles (int 16)
- Vector processor: RISC-V with RVV 1.0
- Custom instructions for softmax and local storage access
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DDR5/4 PHY for Samsung
- Lowest latency for data-intensive applications
- Highest data rates with detailed system guidelines
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Denali Controller for GDDR6
- Compatible with GDDR6 devices compliant to JESD250a
- Supports advanced RAS features including SEC/DED ECC, error scrubbing, parity, etc.
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GDDR6 PHY for Samsung
- Derived from Cadence’s silicon-proven DDR, LPDDR, and high-speed SerDes designs
- Highest data rates with detailed system guidelines
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Secure Execution Processor
- Built-in protection of code and data in a 32-bit compact, low-power, royalty-free, processor IP core.
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64-bit CPU with RISC-V Vector Extension
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- RISC-V vector extension
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64-bit CPU with RISC-V Vector Extension
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- RISC-V vector extension
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Neoverse V3 CPU
- The Fastest Neoverse CPU Ever
- A Platform Built for AI
- Next-Generation Security
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64-bit RISC-V high-performance embedded core
- 64-bit RISC-V high-performance embedded core. Ideal for control/compute/acceleration workloads requiring high performance and 64-bit capabilities.
