Memory subsystem IP

The AXI Performance Subsystem is an AMBA® AXI4 based system that is useful as the digital infrastructure for building SOCs needing high performance.
This system contains an 8 Master component, 16 Slave component AXI4 multi-matrix for supporting multiple high speed user AXI Master components while providing high performance with Cortex-A5 class processors.

Industrial Networking: Rapid packet processing of data through multiple, switched ethernet ports with support for factory automation protocols
5G/6G Communications: Scalable L2/L3 Ethernet switch with flexible port counts/speeds, including TSN and security
Automotive Gateway: High-speed data packet networking with multiple communication interfaces and support for switching and bridging
Datacenter Infrastructure: Standalone data processing units to handle highly multiplexed data streams corresponding to millions of network connections with high efficiency and low power

128/512-bit (16-byte) encryption and decryption per clock cycle throughput
Bidirectional design including separate crypto channels for read and write requests, ensuring non-blocking Read
Read-modify-write supporting narrow burst access.
Zeroization and support for memory initialization
Latency: <28 clock cycles for unloaded READ

Fully synthesizable and configurable memory subsystem IP that enables significant improvement in power, performance and endurance not only for NuRAM but also other third party MRAMs as well as RRAM, PCRAM and Flash

Supports up to 40 Gbps per pin operation
2.5 GHz CK4 clock
1.25 GHz controller clock
Internal data path 32x memory width (i.e. 256 bits for 8-bit memory)
Optimized for high efficiency and low latency across a wide range of traffic scenarios (random/sequential, short/long bursts, etc.)
Optimized command sequence for highest bus utilization including per-bank refresh scheduling: single queue structure handles look-ahead activates/ precharges and read/write ordering for minimal latency

A powerful hardware-based product that is designed for high throughput and high speed.
PQPerform-Lattice adds post-quantum cryptography for applications that handle a large number of transactions, such as high-capacity network hardware applications or HSMs (hardware security modules) requiring fast performance.
It’s designed for performance and supports FIPS 204 ML-DSA digital signatures for quantum-secure authentication and FIPS 203 ML-KEM for quantum-secure key exchange.

Memory Subsystem IP