H8SX is a high speed 32-bit CPU, which is upward-compatible with H8/300, H8/300H and H8S CPUs on an object level.
This subsystem IP supports many and powerful microcontroller functions, including bus controller (BSC), interrupt controller (INT), data transfer controller (DTC), DMA controllers (DMAC and EXDMAC), timers, serial communication interface (SCI) and on-chip debug functions.
Development tools for this IP is common with Renesas H8S microcontroller products.
H8SX CPU subsystem (H8SX C3000) IP
Overview
Key Features
- An original subsystem for SoCs other than microcontrollers
- 3 type interfaces available to connect user functions or IPs
- compiled memory interface
- external memory interface
- peripheral bus interface
- 3 type data transfer functions
- Data transfer controller (DTC)
- Direct memory access controller (DMAC)
- External bus direct memory access controller (EXDMAC)
- 3 type timers
- 16-bit timer pulse unit (TPU)
- 8-bit timer
- Watchdog timer (WDT)
- Programmable pulse generator (PPG)
- Serial communication interface
- Supporting on-chip debug functions (option)
- Applicable to various processes and FPGAs
Block Diagram
Technical Specifications
Related IPs
- H8S CPU subsystem (H8S C200) IP
- I3C Controller IP – I3C / I2C Slave, SCL Clock only, Configure User Registers, no CPU Host Required
- I3C Controller IP – I3C / I2C Slave, Configure User Registers, no CPU Host Required
- Synthesizable 68000 Compatible CPU Core
- Synthesizable 6800 Compatible CPU Core
- High Performance 8051 Compatible CPU Core