H8S is a high speed 16-bit CPU with an internal 32-bit architecture, which is upward-compatible with H8/300 and H8/300H CPUs on an object level.
This subsystem IP supports basic and simple microcontroller functions, including bus controller (BSC), interrupt controller (INT), timers, serial communication interface (SCI) and on-chip debug functions.
Development tools for this IP is common with Renesas H8S microcontroller products.
H8S CPU subsystem (H8S C200) IP
Overview
Key Features
- An original subsystem for SoCs other than microcontrollers
- 3 type interfaces available to connect user functions or IPs
- compiled memory interface
- external memory interface
- peripheral bus interface
- 4 type timers
- 16-bit free-running timer (FRT)
- 8-bit timer
- 14-bit PWM timer
- Watchdog timer (WDT)
- Serial communication interface
- Supporting on-chip debug functions (option)
- Applicable to various processes and FPGAs
- Handy size
Block Diagram
Technical Specifications
Related IPs
- H8SX CPU subsystem (H8SX C3000) IP
- I3C Controller IP – I3C / I2C Slave, SCL Clock only, Configure User Registers, no CPU Host Required
- I3C Controller IP – I3C / I2C Slave, Configure User Registers, no CPU Host Required
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