Memory 22FDX IP
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GF 22FDX 5.5V OTP Auto-Grade1 IO Staggered
- Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs
- Synopsys’ embedded one-time programmable (OTP) non-volatile memory (NVM) IP, based on XHF architecture, enables designers to address these challenges
- Synopsys’ OTP NVM IP architecture provides high levels of security, high yields, low power, and excellent reliability, which is why Synopsys OTP NVM is the leader in antifuse technology with >10B units shipped and availability in more than a dozen foundries
- Synopsys OTP NVM IP is silicon-verified in TSMC N4P, N5, N5A, N6, and N7
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GF 22FDX 5.5V OTP Auto-Grade1 IO Inline
- Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs
- Synopsys’ embedded one-time programmable (OTP) non-volatile memory (NVM) IP, based on XHF architecture, enables designers to address these challenges
- Synopsys’ OTP NVM IP architecture provides high levels of security, high yields, low power, and excellent reliability, which is why Synopsys OTP NVM is the leader in antifuse technology with >10B units shipped and availability in more than a dozen foundries
- Synopsys OTP NVM IP is silicon-verified in TSMC N4P, N5, N5A, N6, and N7
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Single Rail SRAM GLOBALFOUNDRIES 22FDX
- Ultra-low voltage logic designs using adaptive body biasing demand dense SRAM solutions which fully integrate in the ABB aware implementation and sign-off flow of the Racyics® ABX Platform solution.
- The Racyics® Single Rail SRAM supports ultra-low voltage operation down to 0.55 V where logic designs with Minimum-Energy-Point are implemented.
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Dual Rail SRAM Globalfoundries 22FDX
- Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
- Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABB
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Automotive Grade 1 – Wide Range PLL on GLOBALFOUNDRIES 22FDX-AG1
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
- Fully integrated inside customer-specified IO ring
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ComputeRAM
- Available as a 18 kB macro in GlobalFoundries 22FDX process; - Memory Compiler and FinFET variants under development
- Low power sleep mode with data retention
- Built using proven foundry SRAM bit cells, fully CMOS, strictly obeys foundry DFM/DRC rules
- Bit-accurate computation
