MIPI Soundwire PHY IP

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Compare 7 IP from 3 vendors (1 - 7)

MIPI SoundWire Slave Controller 1.2
- MIPI SoundWire®Slave Controller, typically integrated into audio DSP/Codecs or directly into audio peripherals such as Microphones and Amplifiers used in smart phones, tablets and mobile PCs.
- The IP when integrated provides SoundWire, a new audio interface to connect to Master typically embedded in Application Processor or Audio Codecs.
MIPI SoundWire Master Controller 1.2
- Compliant with MIPI SoundWire specification version 1.2
- Configurable number of Data Ports Configurable Direction – Source or Sink
- Implements clock gearbox with programmable frequency divider
- Implements SoundWire Bus Clock Stop and WakeUp detection
Simulation VIP for MIPI SoundWire
- Multi-lane Payload Transport
- Up to 8 data lanes are supported
- High-PHY Mode
- High-performance PHY
MIPI SoundWire I3S Verification IP
- Full MIPI SoundWire I3S Master, Slave and Monitor functionality
- Supports MIPI Soundwire-I3S Bus Draft Specification v0.4r06.
- Supports system with one master and one or more slaves (upto 8 slaves).
- Supports LVDS PHY for higher speed and a single-ended CMOS PHY for lower speed systems.
MIPI SoundWire Verification IP
- Full MIPI SoundWire Master, slave and Monitor functionality
- Supports MIPI SoundWire version 1.2r08 Specifications
- Supports Basic PHY and High PHY mode
- Supports IO timing
MIPI SOUNDWIRE Synthesizable Transactor
- Supports MIPI SoundWire version 1.2r08 Specifications
- Supports full MIPI SoundWire Master,Slave functionality
- Supports Basic PHY and High PHY mode
- Supports IO timing
MIPI SOUNDWIRE PSVIP
- Supports MIPI SoundWire version 1.2r08 Specifications
- Supports full MIPI SoundWire Master,Slave functionality
- Supports Basic PHY and High PHY mode
- Supports IO timing