MIPI Soundwire PHY IP
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8
IP
from 3 vendors
(1
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8)
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MIPI Soundwire PHY
- MIPI specification for SoundWire V1.2
- TSMC 12nm FFC
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Simulation VIP for MIPI SoundWire
- Multi-lane Payload Transport
- Up to 8 data lanes are supported
- High-PHY Mode
- High-performance PHY
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MIPI SoundWire I3S Verification IP
- Full MIPI SoundWire I3S Master, Slave and Monitor functionality
- Supports MIPI Soundwire-I3S Bus Draft Specification v0.4r06.
- Supports system with one master and one or more slaves (upto 8 slaves).
- Supports LVDS PHY for higher speed and a single-ended CMOS PHY for lower speed systems.
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MIPI SoundWire Verification IP
- Full MIPI SoundWire Master, slave and Monitor functionality
- Supports MIPI SoundWire version 1.2r08 Specifications
- Supports Basic PHY and High PHY mode
- Supports IO timing
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MIPI SOUNDWIRE Synthesizable Transactor
- Supports MIPI SoundWire version 1.2r08 Specifications
- Supports full MIPI SoundWire Master,Slave functionality
- Supports Basic PHY and High PHY mode
- Supports IO timing
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MIPI SOUNDWIRE PSVIP
- Supports MIPI SoundWire version 1.2r08 Specifications
- Supports full MIPI SoundWire Master,Slave functionality
- Supports Basic PHY and High PHY mode
- Supports IO timing
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MIPI SoundWire Slave Controller 1.1
- Compliant with latest draft MIPI SoundWire specification version 1.0
- Flexible configuration for optimal gate count and power
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MIPI SoundWire Master Controller 1.1
- Compliant with latest draft MIPI SoundWire specification version 1.0
- Configurable number of Data Ports
- Multi-lane Support with flexible Port <-> Lane mapping
