IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI Controller IP > MIPI SoundWire IP > MIPI SoundWire Verification IP

MIPI SoundWire Verification IP

Overview

The SmartDV Verification IP (VIP) for MIPI SoundWire provides an efficient and simple way to verify the MIPI SoundWire protocol bus. The SmartDV VIP for MIPI SoundWire is fully compliant version 1.2r08 MIPI SoundWire Bus Specification.

MIPI SoundWire Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI SoundWire Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Full MIPI SoundWire Master, slave and Monitor functionality
  • Supports MIPI SoundWire version 1.2r08 Specifications
  • Supports Basic PHY and High PHY mode
  • Supports IO timing
  • Supports all frame shapes
  • Supports static, dynamic and PHY frame synchronization
  • Supports handling over bus control to Monitor based on BREQ bit
  • Supports BANK handling
  • Supports handling of all combinations of ACK/NACK responses
  • Supports PING, Read, Write commands
  • Supports all registers definitions with proper read/write attributes
  • Supports Dual Ranked Register and Commit mechanism
  • Supports Multi-byte Quantities buffer
  • Supports dynamic shape and payload switching
  • Supports groups and group response generation and handling
  • Supports bulk payload transport and bulk register access
  • Supports PRBS, Static0 and Static1 test modes
  • Supports bus clock speed encoding
  • Supports clock pause and clock stop operation
  • Supports various kind of interrupts
  • Supports multi-lane payload transport
  • Supports various kind of payload positioning w.r.t Block per port and Block per channel
  • Supports various kind of flow controlled payload transport
  • Supports various kind of reset's
    • Bus-Reset
    • ClockStopMode1 Reset
    • LostSync Reset
    • Register Reset
  • Supports various kind of Master and Slave errors generation and detection
    • Parity errors
    • CRC errors
    • Dynamic Sync bit errors
    • Static sync bit errors
    • Slave responding when address not assigned
    • Master startup using wrong shape
    • Bus clash error
    • PRBS pattern error
    • Testmode Static 0 error
    • Testmode Static 1 error
  • Status counters for various events in bus
  • Detects and notifies the test bench of all protocol and timing errors
  • Callbacks in master, slave and monitor for user processing of data
  • MIPI SoundWire Verification IP comes with complete test suite to test every feature of MIPI SoundWire specification
  • Functional coverage for complete MIPI SoundWire features

Benefits

  • Faster testbench development and more complete verification of MIPI SoundWire designs.
  • Easy to use command interface simplifies testbench control and configuration of master and slave.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

MIPI SoundWire Verification IP Block Diagram

Deliverables

  • Complete regression suite containing all the MIPI SoundWire testcases.
  • Examples showing how to connect various components, and usage of Master,Slaves and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

Request Info

Related IPs

×
Semiconductor IP