Mipi d-phy receiver IP

Compare 67 IP from 23 vendors (1 - 10)

MIPI D-PHY Receiver for CSI-2 of TSMC 40nm LP
- Renesas MIPI D-PHY Receiver can be used for analog Receiver of following interface.
- Technology is TSMC 40nm LP 1p8M (4x2y1z).
- Supply voltage can be applied 1.18V for core voltage, 1.8V for IO voltage.
- Maximum data rate of each channel is 1.0Gbps at High-speed mode.
Camera MIPI D-PHY Receiver 4.5Gbps 4-Lane
- The CL12632M4R1AS1BIP4500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) and DSP.
- The CL12632M4R1AS1BIP4500 is designed to support data rate in excess of maximum 4.5Gbps utilizing MIPI D-PHY v2-1 interface specification.
MIPI Receiver,DPHY RX V1.2; UMC 28nm HPC Logic and Mixed-Mode Process
MIPI Receiver, DPHY V1.2 RX ; UMC 28nm HPC process
MIPI Receiver, DPHY V1.1 RX ; UMC 28nm HPC process
MIPI DPHY Receiver on GF55LPe
- MIPI D-PHY version 1.2 compliant PHY receiver
- Consists of 4 data lane and 1 clock lane
MIPI D-PHY Receiver IP, 80Mbps - 1.5Gbps, UMC 40nm LP process
MIPI D-PHY Receiver IP, 80Mbps - 1.5Gbps, UMC 55nm SP process
MIPI D-PHY Receiver IP, 80Mbps - 1Gbps, UMC 40nm LP process
MIPI D-PHY Receiver IP, 80Mbps - 1Gbps, UMC 40nm LP process

MIPI D-PHY Receiver IP