MIPI DPHY Receiver on GF55LPe

Overview

Key Features

• MIPI D-PHY version 1.2 compliant PHY receiver
• Consists of 4 data lane and 1 clock lane
• Supports HS mode (80Mbps to 1.5Gbps) and LS mode (up to 10Mbps)
• Integrated control interface logic to supports PHY Protocol Interface (PPI)
• Integrated 100-ohm termination resistors with common-mode biasing
• Configurable analog characteristics
• Timing skew
• Terminator resistance
• BGR voltage
• 1.2V power supply
• Support GlobalFoundry 55nm LPe process

Block Diagram

Deliverables

• Verilog RTL or netlist source code of lane control unit
• Liberty timing models for synthesis and STA
• Timing constrains for synthesis and physical layout
• Verilog behavior model of PHY part
• Physical design database
• Integration guidelines

Technical Specifications