MIPI D-PHY Receiver IP, 80Mbps - 1Gbps, UMC 40nm LP process
Overview
MIPI Receiver 80Mbps-1Gbps, Combo PHY for MIPI & HiSPi & LVDS & SubLVDS, UMC 40nm LP Low-K Logic process, Two Lane.
Technical Specifications
Short description
MIPI D-PHY Receiver IP, 80Mbps - 1Gbps, UMC 40nm LP process
Vendor
Vendor Name
Foundry, Node
UMC 40nm LP
UMC
Pre-Silicon:
40nm
LP
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