IP Catalog > MIPI C-PHY/ D-PHY Combo

MIPI C-PHY/ D-PHY Combo IP

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Compare 60 IP from 11 vendors (1 - 10)
  • MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY - 14nm, 8nm, 5nm, 4nm
    • The MIPI D-PHY/C-PHY Combo IP is a hard-macro PHY for CSI RX or DSI TX. IO pads and ESD structures are included.
    • In addition, extensive built-in self-test features, such as loopback and scan, are supported.
    • It offers a cost-effective and low-power solution.
    Block Diagram -- MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY - 14nm, 8nm, 5nm, 4nm
  • MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP in TSMC
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    Block Diagram -- MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP in TSMC
  • MIPI D-PHY Rx IP, Silicon Proven in TSMC 12FFC
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    • Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
    • Support LS data rate of 10Mbps and Ultra-low power mode
    Block Diagram -- MIPI D-PHY Rx IP, Silicon Proven in TSMC 12FFC
  • MIPI D-PHY Tx IP, Silicon Proven in TSMC 12FFC
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    • Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
    • Support LS data rate of 10Mbps and Ultra-low power mode
    Block Diagram -- MIPI D-PHY Tx IP, Silicon Proven in TSMC 12FFC
  • MIPI D-PHY Rx IP, Silicon Proven in TSMC 7FF
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    • Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
    • Support LS data rate of 10Mbps and Ultra-low power mode
    Block Diagram -- MIPI D-PHY Rx IP, Silicon Proven in TSMC 7FF
  • MIPI D-PHY Tx IP, Silicon Proven in TSMC 7FF
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    • Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
    • Support LS data rate of 10Mbps and Ultra-low power mode
    Block Diagram -- MIPI D-PHY Tx IP, Silicon Proven in TSMC 7FF
  • MIPI C-PHY/D-PHY Combo IP
    • The MIPI C/D-PHY combo IP is a high-frequency low-power, low cost, physical layer compliant with the MIPI® Alliance Standard for C-PHY and D-PHY.
    • The PHY can be configured as a MIPI Master or MIPI Slave, supporting camera interface CSI-2 v1.2 or display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-2 v1.0 applications in the C-PHY mode.
    Block Diagram -- MIPI C-PHY/D-PHY Combo IP
  • MIPI C/D Combo TX PHY and DSI controller
    • High Data Rates: Supports data transmission rates
    • Energy Efficiency: Optimized for low power consumption, making it ideal for battery-powered devices
    • Complete Solution: Combines the MIPI CD-PHY Transmitter PHY and DSI Controller to make it a one-stop solution
    • Flexible IP Configuration




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  • MIPI C/D Combo PHY RX - GlobalFoundries 22FDX
    • Supports up to one clock lane and four data lanes for DPHY1.2
    • Fully compliant with MIPI D-PHY v1.2 and C-PHY v1.0 spec
    • Available in GlobalFoundries 22FDX process
    • Three 3phase encoded data lanes for CPHY1.0
    Block Diagram -- MIPI C/D Combo PHY RX - GlobalFoundries 22FDX
  • MIPI C/D Combo PHY TX
    • Supports HS TX data rate up to 2.5Gbps (2.5Gsps) per lane (trio)
    • Fully compliant with MIPI D-PHY v1.2 and C-PHY v1.0 spec
    • Available in GlobalFoundries 22FDX process
    • Three 3phase encoded data lanes for CPHY1.0
    Block Diagram -- MIPI C/D Combo PHY TX
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