MIPI C/D Combo PHY TX

Overview

The C/D Combo PHY TX IP can be flexibly configured as DPHY or CPHY, which offers a compatibility with the DPHY only design, and a more cost-effective and power-efficiency design with CPHY. With CPHY V1.0 the maximum channel rate achieved would be 3Gsps which would result in an effective data rate of 6.85Gbps.CPHY reuses the similar Low power signaling same as the DPHY. CPHY is designed such a way that it can co-exist sharing the same lines as DPHY. CPHY/DPHY combo IPs will be compatible to operate on the same channels used by DPHY, which offer a much wider area of application and flexibility. It can work with both old DPHY systems and is compatible with new CPHY.

 

Key Features

  • Supports HS TX data rate up to 2.5Gbps (2.5Gsps) per lane (trio)
  • Fully compliant with MIPI D-PHY v1.2 and C-PHY v1.0 spec
  • Available in GlobalFoundries 22FDX process
  • Three 3phase encoded data lanes for CPHY1.0
  • Built-in self test function
  • Junction temperature range: -40°C~25°C~125°C
  • Supports up to one clock lane and four data lanes for DPHY1.2
  • Supports LS TX ULPS, LPDT and reverse direction for DSI TX with command mode application
  • Can be configured as D-PHY or C-PHY flexible
  • Supports LS TX data rate of 10Mbps
  • Supply voltage: 1.8V±10%, 0.8V±10%
  • Support wire-bond and flip-chip package type

Block Diagram

MIPI C/D Combo PHY TX Block Diagram

Technical Specifications

Foundry, Node
GlobalFoundries 22FDX process
GLOBALFOUNDRIES
Pre-Silicon: 22nm FDX
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Semiconductor IP