MIPI D-PHY Tx IP, Silicon Proven in TSMC 7FF
Overview
Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes. Users are able to configure this Combo PHY into either D-PHY or C-PHY mode to support different applications. It is also compliant with the PPI interface, which allows seamless integration with either CIS-2 or DSI controller. D-PHY and C/D-PHY Combo in various processes across foundries, with the most competitive PPA (Performance, Power, and Area) and standard compliances. In addition to a long list of features, the MIPI D-PHY is already ISO 26262 ASIL-B certified for automotive multimedia applications.
Key Features
- Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
- Support both MIPI DSI and CSI-2 protocols
- Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
- Support LS data rate of 10Mbps and Ultra-low power mode
- Support fast lane turnaround (FTA) and alternate low-power (ALP) mode
- Support D-PHY mode with 1 clock lane & up to 4 data lanes
- Support C-PHY mode up to 3 trios for TX and 4 trios for RX
- Support TX-EQ and Rx-EQ function to compensate loss of a long channel
- Support additional D-PHY RX mode with 2 sets of (1 clock lane and up to 2 data lanes)
- Support additional C-PHY RX mode with 2 sets of 2 trios
- Provide D-PHY clock and data lane swap function
- Provide C-PHY trios swap function
- Provide a stand-alone at-speed multi-lanes (trios) parallel BIST module for mass production tests
- Silicon proven in 7FF
Block Diagram
Deliverables
- GDSII & layer map
- Place-Route views (.LEF)
- Liberty library (.lib)
- Verilog behaviour model
- Netlist & SDF timing
- Layout guidelines, application notes
- LVS/DRC verification reports
Technical Specifications
Maturity
In Production
Availability
Immediate