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MACsec IPSEC IP

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Search (29)
Compare 29 IP from 8 vendors (1 - 10)
  • 1.6T/3.2T Multi-Channel MACsec Engine with TDM Interface (MACsec-IP-364)
    • The MACsec-IP-364 is a MACsec/IPsec engine developed specifically for high-speed, multi-rate and multi-port Ethernet devices.
    • Its architecture provides an optimal multi-protocol solution for aggregate throughput for 1.6T and 3.2T.
    • The MACsec-IP-364 is ideal for deployment in data center, enterprise and carrier network applications, as well as network-attached high-performance computing.
    Block Diagram -- 1.6T/3.2T Multi-Channel MACsec Engine with TDM Interface (MACsec-IP-364)
  • 800G Multi-Channel MACsec Engine with TDM Interface
    • Complete and fully compliant MACsec Packet Engine with classifier and transformation engines for rates of 100 to 800 Gbps, up to 64 channels, ready for FlexE
    • All IEEE MACsec standards supported (including IEEE802.1AE-2018). Optional inclusion of Cisco extensions, IPsec ESP tunnel and transport mode with AES-GCM cipher
    • Supplied with the Driver Development Kit to accelerate time to market. Rambus offers MACsec Toolkit for IEEE 802.1X key management
    Block Diagram -- 800G Multi-Channel MACsec Engine with TDM Interface
  • IEEE 802.1ae MACSEC IP Core for 40 Gbit Ethernet
    • Complies with IEEE 802.1ae standard
    • Based on the Algotronix AES-GCM-40G product
    • Supports 256 bit keys as standard
    • Targets high performance FPGA families from Xilinx and Altera.
  • IEEE 802.1ae MACSEC IP Core for 10 Gbit Ethernet
    • Complies with IEEE 802.1ae standard
    • Based on the Algotronix AES-GCM-1G product
    • Supports 128 bit keys as standard, with 256 bit key option available
    • Targets all modern FPGA families from Xilinx, Altera, Microsemi and Lattice
  • Multiple SecY IEEE 802.1ae MACSEC IP Core for 40Gbit Ethernet
    • Complies with IEEE 802.1ae standard
    • Based on the Algotronix AES-GCM-1G product
    • Supports 128 bit keys as standard, with 256 bit key option available
    • Targets all modern FPGA families from Xilinx, Altera, Microsemi and Lattice
  • Ethernet Switch/Router IPSec/MACSec 9x10G + 2x40G
    • 9 ports of 10 Gigabit Ethernet.
    •  2 ports of 40 Gigabit Ethernet.
    •  Full wire-speed on all ports and all Ethernet frame sizes.
    •  Store and forward shared memory architecture.
    •  Support for jumbo packets up to 32733 bytes.
    Block Diagram -- Ethernet Switch/Router IPSec/MACSec 9x10G + 2x40G
  • Symmetric Cryptographic Intel® FPGA IP
    • The Symmetric Cryptographic Intel® FPGA IP is a hard IP core implementing AES and SM4 encryption and decryption
    • Typically, the AES and SM4 standards are used to protect the confidentiality of network data in 5G, data center, and IoT applications, but can be used to secure any high-speed data in transit
    • Additionally, the XTS profile can be used in data storage applications.
    Block Diagram -- Symmetric Cryptographic Intel® FPGA IP
  • Ethernet - up to 800G Verification IP
    • Supports 2.5G and 5G Speeds as per 802.3cb
    • 2.5GBASE-KX
    • 5GBASE-KR
    • 2.5GBASE-T
    Block Diagram -- Ethernet - up to 800G Verification IP
  • Ethernet 200G,400G Verification IP
    • Supports 200G,400G interfaces as per the specifications defined in IEEE 802.3bs
    • Supports 200GMII and 400GMII
    • Supports 200GXS and 400GXS
    • 200GBase_KR8
    Block Diagram -- Ethernet 200G,400G Verification IP
  • 200GBase-KR8/KR4/KR2 Verification IP
    • Supports 200GBase-KR8/KR4/KR2 interfaces as per the specifications defined in IEEE 802.3bs
    • Supports scrambler
    • Supports FEC
    • Supports CDAUI_16
    Block Diagram -- 200GBase-KR8/KR4/KR2 Verification IP
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