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Lightweight Multi-Format Video Encoder IP

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Compare 107 IP from 31 vendors (1 - 10)
  • Lightweight and Configurable Root-of-Trust Soft IP
    • QRoot Lite™ is a silicon IP solution designed specifically for resource-constrained MCUs and IoT devices. It provides essential security capabilities including secure boot, device attestation, and sealed storage.
    • Built on the industry-standard TCG MARS specification, QRoot Lite™ simplifies integration, reduces costs, and accelerates your journey toward regulatory compliance and trusted embedded products.
    Block Diagram -- Lightweight and Configurable Root-of-Trust Soft IP
  • NIST’s ASCON Lightweight Crypto Algorithm Accelerator
    • The ASCON-IP-41 is an efficient implementation of NIST’s lightweight crypto algorithm family ASCON. ASCON is a single algorithm defined in different modes to support AEAD and HASH operations.
    • As a multi-purpose algorithm with minimal area requirements ASCON is extremely suitable for low-cost and low-power applications.
  • Cryptographic co-processor for lightweight cryptography
    • Support AES-XTS mode — IEEE Std 1619-2007 standard compliance
    • Support 128 and 256-bit key size
    • Random memory block access support
  • Ascon, A Lightweight Cryptographic Suite for AEAD and Hashing
    • Small Resource Requirements
    • Versatile Algorithm Support
    • Secure Architecture
    Block Diagram -- Ascon, A Lightweight Cryptographic Suite for AEAD and Hashing
  • SDI Mapper for TICO-RDD35 & TicoXS (JPEGXS) lightweight codecs
    • Manage both the TX & RX
    • Manage the insertion of the TICO-RDD35 or JPEG-XS detection box over the active area of the SDI
    Block Diagram -- SDI Mapper for TICO-RDD35 & TicoXS (JPEGXS) lightweight codecs
  • TICO Lightweight HD Encoder
    • Visually Lossless quality up to 4:1
    • 4:2:2 ; 4;4:4 & 8,10,12bit
    • CBR (VBR as option)
  • TICO Lightweight HD Decoder
    • Visually Lossless quality up to 4:1
    • 4:2:2 ; 4;4:4 & 8,10,12bit
    • CBR (VBR as option)
  • Lightweight Configurable Display Controller
    • Fully programmable clock and timing control for flat panel displays with progressive scanning
    • Support for resolutions up to 4096×4096
    • Completely variable timing parametersfor standard or specific display resolutions
    • Support for 8,1618 or 24 bit RGB output color depth
    Block Diagram -- Lightweight Configurable Display Controller
  • Low power 32-bit processor with lightweight computing power
    • Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set);
    • Pipeline: 3 to 4-stage variable length pipeline;
    • General register: 32 32-bit GPRs;
    • Bus interface: Tri-bus (instruction bus + data bus + system bus);
    Block Diagram -- Low power 32-bit processor with lightweight computing power
  • Serial Lite II Intel® FPGA IP Core
    • The Serial Lite II Intel® FPGA IP core provides a simple and lightweight way to move data from one point to another reliably at high speeds
    • It consists of a serial link of up to 16 bonded lanes with logic to provide a number of basic and optional link support functions
    • The Atlantic* interface is the primary access for delivering and receiving data.
    Block Diagram -- Serial Lite II Intel® FPGA IP Core
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Semiconductor IP