Lightweight Multi-Format Video Encoder IP
Filter
Compare
117
IP
from 31 vendors
(1
-
10)
-
Lightweight and Configurable Root-of-Trust Soft IP
- QRoot Lite™ is a silicon IP solution designed specifically for resource-constrained MCUs and IoT devices. It provides essential security capabilities including secure boot, device attestation, and sealed storage.
- Built on the industry-standard TCG MARS specification, QRoot Lite™ simplifies integration, reduces costs, and accelerates your journey toward regulatory compliance and trusted embedded products.
-
NIST’s ASCON Lightweight Crypto Algorithm Accelerator
- The ASCON-IP-41 is an efficient implementation of NIST’s lightweight crypto algorithm family ASCON. ASCON is a single algorithm defined in different modes to support AEAD and HASH operations.
- As a multi-purpose algorithm with minimal area requirements ASCON is extremely suitable for low-cost and low-power applications.
-
Cryptographic co-processor for lightweight cryptography
- Support AES-XTS mode — IEEE Std 1619-2007 standard compliance
- Support 128 and 256-bit key size
- Random memory block access support
-
Ascon, A Lightweight Cryptographic Suite for AEAD and Hashing
- Small Resource Requirements
- Versatile Algorithm Support
- Secure Architecture
-
SDI Mapper for TICO-RDD35 & TicoXS (JPEGXS) lightweight codecs
- Manage both the TX & RX
- Manage the insertion of the TICO-RDD35 or JPEG-XS detection box over the active area of the SDI
-
TICO Lightweight HD Encoder
- Visually Lossless quality up to 4:1
- 4:2:2 ; 4;4:4 & 8,10,12bit
- CBR (VBR as option)
-
TICO Lightweight HD Decoder
- Visually Lossless quality up to 4:1
- 4:2:2 ; 4;4:4 & 8,10,12bit
- CBR (VBR as option)
-
Lightweight Configurable Display Controller
- Fully programmable clock and timing control for flat panel displays with progressive scanning
- Support for resolutions up to 4096×4096
- Completely variable timing parametersfor standard or specific display resolutions
- Support for 8,1618 or 24 bit RGB output color depth
-
Low power 32-bit processor with lightweight computing power
- Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set);
- Pipeline: 3 to 4-stage variable length pipeline;
- General register: 32 32-bit GPRs;
- Bus interface: Tri-bus (instruction bus + data bus + system bus);
-
PCIe Gen 6 controller IP
- Designed to the latest PCI Express 6.0 (64 GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s), and PIPE 6.x (8, 16, 32, 64 and 128-bit) specifications
- Supports SerDes Architecture PIPE 10b/20b/40b/80b width
- Supports original PIPE 8b/16b/32b/64b/128b width
