8b-10b Verification IP

Overview

The 8b-10b Verification IP provides an effective &efficient way to verify the 8b-10b components of an IP or SoC. The VIP is fully compliant with the 8b-10b Specification. The VIP is lightweight with easy plug-and-play components so that there is no hit on the design cycle time

Key Features

  • Encoding of 8-bit bytes into 10-bit symbols.
  • Decoding of 10-Bit symbols into 8-bit Bytes.
  • Encoding of 12 special (K) characters in addition to the 256 possible combinations.
  • Encoder tracks running disparity, ensuring that consecutive symbols have correct disparity.
  • Industry-compatible special character coding.
  • Supports continuous transmission with a balanced number of zeros and ones in the code stream (DC Balancing).
  • It supports Gen 1 PHY operating at 5Gbps.
  • Technologies that are used 8b-10b
    • DisplayPort
    • PCI Express
    • USB 3.0
    • Thunderbolt
    • Ethernet
    • SATA l M-PHY

Benefits

  • Available in native System Verilog (UVM/OVM/VMM) and Verilog
  • Unique development methodology to ensure the highest levels of quality
  • Availability of Compliance & Regression Test Suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and coverage points with connectivity examples for all the components
  • Consistency of interface, installation, operation, and documentation across all our VIPs
  • Provide complete solutions and easy integration in IP and SoC environment

Block Diagram

8b-10b Verification IP   
 Block Diagram

Deliverables

  • 8b-10b Encoder BFM
  • 8b-10b Decoder BFM
  • 8b-10b Monitor
  • Testbench Configurations
  • Test Suite (Available in Source code)
    • Basic and Directed Protocol Tests
    • Random Tests and Error Scenario Tests
    • Assertions & Cover Point Tests
  • Integration Guide, User Manual, and Release Notes

Technical Specifications

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