LVDS IP
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468
IP
from 58 vendors
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10)
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Bi-Directional LVDS with LVCMOS
- TIA/EIA644A LVDS and sub-LVDS compatibility
- Receiver also compatible with LVPECL
- Operates over 2Gbps and up to 3Gb/s in some processes
- Trimmable on-die termination, can be enabled while Tx is operating for better signal integrity
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LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
- Process: Silterra 0.16um CMOS 1P5M Process
- Supply Voltage Range: AVDD33 = 3.3v +/-10%, AVDD18 = 1.8v +/-10%
- Ambient Temperature: 0°C~80°C
- Compatible with BLVDS_25 of Spartan-3A FPGA
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MIPI DPHY & LVDS Transmit Combo on GF55LPe
- MIPI D-PHY version 1.2 compliant PHY transmitter
- OpenLDI version 0.9 compliant LVDS transmitter
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Four Channel (4CH) LVDS in TSMC 40LP
- Compatible with TIA/EIA-644 LVDS Standard
- 175 Mbps - 1000 Mbps bandwidth/channel
- Up to 4 Gbps data throughput
- 7-bit/10-bit serial data transmitted per pixel clock per channel
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Four Channel (4CH) LVDS Receiver in TSMC 40LP
- Compatible with TIA/EIA-644 LVDS Standard
- Consists of 1 Clock lane and up to 4 Data lanes
- Up to 1.0 Gbps bandwidth per channel
- Up to 4.0 Gbps data throughput
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Library of LVDS IOs cells for TSMC 65LP
- TSMC 65 LP
- 2.5V/1.2V IO/Core transistors
- Fully compliant with TIA/EIA-644-A-2001
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Library of LVDS IOs cells for TSMC 40LP
- TSMC 40 LP
- 2.5V/1.1V IO/Core transistors
- Fully compliant with TIA/EIA-644-A-2001
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High speed universal LVDS Transceiver
- Up to 1 GHz operation (2 Gbs)
- Novel equalization with programmable emphasis
- Compensation block provides PVT-invariance
- Built-n termination resistors
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LVDS RX & TX IOs in multiple foundry technology
- LVDS TX
- LVDS RX
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A 65nm Wirebond IO library with 2.5V GPIO, LVDS TX & RX and 2.5V analog / RF
- GPIO:
- LVDS TX & RX
- ANALOG / RF
- Physical Attributes
