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Compare 130 IP from 24 vendors (1 - 10)
  • LDPC Intel® FPGA IP
    • Low-density parity-check (LDPC) codes are linear error correction codes that allow you to transmit messages over noisy channels.
    • Intel's 5G Low-Density Parity Check (LDPC) Intel FPGA Intellectual Property (IP) core is a high-throughput encoder or decoder that is compliant with 3rd Generation Partnership Project (3GPP) 5G specification.
    Block Diagram -- LDPC Intel® FPGA IP
  • 5G LDPC Intel® FPGA IP
    • Low-density parity-check (LDPC) codes are linear error correcting codes that help you to transmit and receive messages over noisy channels
    • The 5G LDPC and LDPC-V Intel® FPGA IP implement LDPC codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration in your wireless design.
    • LDPC codes offer better spectral efficiency than Turbo codes and support the high throughput for 5G new radio (NR).
    Block Diagram -- 5G LDPC Intel® FPGA IP
  • DVB-S2X Wideband LDPC/ BCH Encoder
    • Compliant with ETSI EN 302 307’
    • Compliant with ETSI EN 302 307-2’
    • Supports BCH-LDPC all code rates for digital video broadcasting
  • LDPC Encoder/Decoder IP Core
    • IPM-LDPC for NandFlash Storage: Adaptable BER, Up to 6 checks per bit, customizable data path
    • IPM-LDPC for short code: option to be full asynchronous, option to be in 3 clock cycles
    • fully configurable: matrix generator, data path, number of iteration checks, packet size
    Block Diagram -- LDPC Encoder/Decoder IP Core
  • LDPC (1723,2048) IIP
    • Compliant with IEEE Standard 802.3.2018 Ethernet specification.
    • Supports full LDPC functionality.
    • Supports the Lower density parity check (1723,2048).
    • Supports the parity generation of 325 bits.
    Block Diagram -- LDPC (1723,2048) IIP
  • eMMC LDPC Encoder/Decoder
    • Supports data rates from 50 MB/s to 9.0 GB/s.
    • Enables custom LDPC core development for specific requirements.
    • Wide range of codeword sizes.
    • Maximum supported parity.
    Block Diagram -- eMMC LDPC Encoder/Decoder
  • LDPC Decoder for 5G NR and Wireless
    • The 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance.
    • It employs the Min-Sum LDPC decoding algorithm to ensure efficient decoding.
    • The core allows for programmable internal bit widths at compile time, though the default values are usually sufficient.
    Block Diagram -- LDPC Decoder for 5G NR and Wireless
  • DVB-S2X Wideband LDPC BCH Decoder
    • Improved performance
    • Improved efficiency w.r.t. Shannon’s limit
    • Finer gradation of code rate and SNR
  • (2048,1723) LDPC decoder for IEEE 802.3an 10GBASE-T
    • Strong error correction performance
    • Optimized method significantly lower the error floor at minimal cost
    • High throughput with low complexity hardware
    • Early termination technique
  • 5G-NR LDPC Encoder
    • High-throughput design.
    • Low-power and low-complexity design.
    • Block-to-block on-the-fly configuration.
    • AXI4-Stream handshaking interfaces for seamless integration.
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