Low-density parity-check (LDPC) codes are linear error correction codes that allow you to transmit messages over noisy channels. Intel's 5G Low-Density Parity Check (LDPC) Intel FPGA Intellectual Property (IP) core is a high-throughput encoder or decoder that is compliant with 3rd Generation Partnership Project (3GPP) 5G specification. LDPC codes offer better spectral efficiency and support the high throughput for 5G new radio (NR). With the flexibility of Intel FPGAs, various configurations can be designed and implemented and re-designed to support any changes to base graph, code rate, Z and LR width.
Features
All Decoders Have:
- MATLAB models
- Double-buffered architecture to reduce latency and boost throughput
- Early stopping criterion
- Parameters for:
- Input parallelism
- Decoding parallelism
- LLR width
- Attenuation factor
