The eMMC LDPC Encoder/Decoder is an advanced flash reliability solution engineered to maximize flash endurance and retention. Featuring industry leading LDPC error correction technology, it delivers superior performance with the lowest power consumption and a compact footprint. Tailored for diverse applications, it supports ultra-low power requirements for mobile devices like smartphones and tablets, while meeting high-performance demands for enterprise SSDs, offering a scalable, customizable platform for a wide range of flash storage needs.
eMMC LDPC Encoder/Decoder
Overview
Key Features
- Supports data rates from 50 MB/s to 9.0 GB/s.
- Enables custom LDPC core development for specific requirements.
- Wide range of codeword sizes.
- Maximum supported parity.
- High parallelism for high data-rate applications.
- Multiple memory access options.
- Supports eASIC, FPGA, and ASIC nodes.
- Simultaneous parity support.
- Concurrent support for multiple LDPC codes.
- On-the-fly LDPC code switching.
- Low area and power consumption.
Benefits
- Supports data rates ranging from 50 MB/s to 9.0 GB/s per LDPC instance.
- Offers a scalable platform for developing custom LDPC cores tailored to specific applications.
- Wide range of codeword sizes with maximum supported parity for diverse requirements.
- High degree of parallelism optimized for high data-rate applications.
- Compatible with multiple platforms, including eASIC, FPGA, and ASIC nodes from 40nm to 10nm.
- Simultaneous support for multiple LDPC codes and parity configurations.
- On-the-fly switching between LDPC codes for dynamic operational flexibility.
- Patented technology ensures industry-leading reliability, performance, and low power for next-gen flash controllers.
Block Diagram
Deliverables
- Source Code for LDPC Compiler.
- Source Code for LDPC Matrix Generation Software.
- FPGA based LLR generation reference design with MATLAB interface.
- UVM verification environment with encoder, error injector, and decoder instantiate.
- Documentation
- IP User Guide.
- Synthesis Guide.