Jesd204c IP

Compare 24 IP from 8 vendors (1 - 10)

JESD204C Transmitter IIP
- Compliant with JESD204 specification JESD204A, JESD204B.01 and JESD204C.
- Full JESD204C transmit functionality.
- Supports data rate upto 32 Gbps.
- Supports programmable clock frequency up to 32 GHz.
JESD204C Receiver IIP
- Compliant with JESD204 specification JESD204A, JESD204B.01 and JESD204C.
- Full JESD204C receive functionality.
- Supports data rate upto 32 Gbps.
- Supports programmable clock frequency up to 32 GHz.
JESD204C Transmitter and Receiver
- With the addition of error correction and Detection(FEC, CRC), cutting-edge instrumentation and other applications can operate without any errors.
- Offers better DC balance, clock recovery and data alignment compared to JESD204B.
- The bit overhead is 3.125% which is much smaller than JESD204B (~ 25%).
- Provides interface for serializing devices from some system designs, reducing space, power, and cost.
JESD204C Controller IP
- Designed to JEDEC JESD204C.1 specification
- Line rates from 1 Gbps to 32.5 Gbps
- Supports 1-24 lanes
- Supports 1-96 converters
JESD204 Verification IP
- This JESD204 Verification IP provides an advanced and efficient solution for verifying and debugging these standards in a UVM simulation environment.
- The verification IP helps reduce time to test, accelerate verification process and ensures a high quality for the end-product.
Simulation VIP for JESD204
- Topology
- Transmitter or receiver configuration
- Clock Frequency
- Any frequency is supported, as the VIP works on the source clock
JESD204 Verification IP
- Follows JESD204 specification JESD204A, JESD204B, JESD204C and JESD204D.
- Supports Transmitter and Receiver Mode.
- Supports data interfaces up to 116 Gbps with PAM4 and up to 58 Gbps with PAM2 in PHY layer.
- Supports up to 32 lanes.
JESD204 Synthesizable Transactor
- Follows JESD204 specification JESD204A, JESD204B and JESD204C
- Supports Transmitter and Receiver Mode
- Supports up to 32 lanes
- Supports 32bit data width per converter
JESD204 CYCLIC FEC IIP
- Compliant with JESD204 specification JESD204C.
- Supports Full JESD204C FEC functionality.
- This FEC(Forward Error correction) methodology implements the (2074, 2048) binary cyclic code is shortened from the cyclic Fire code (8687, 8661).
- Supports FEC of 26 bits parity bits.
JESD204D Verification IP
- Truechip JESD204D VIP is compliant to the latest JESD204D,C.01,C &B specification by JEDEC
- It is also backward compatible with all the previous versions of JESD204
- Supports a wide range configurations for data converter devices
- Over single and multiple serial links with each link can support single or multiple lanes as per requirements

JESD204C IP