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JESD204C IP

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Compare 17 IP from 5 vendors (1 - 10)
  • JESD204C
    • Standard version: JESD204C, Dec 2017
    • Versions Available: Transmitter / Receiver
    • Silicon Agnostic: Targets ASIC, ASSP, FPGA
    Block Diagram -- JESD204C
  • JESD204C Transmitter and Receiver
    • With the addition of error correction and Detection(FEC, CRC), cutting-edge instrumentation and other applications can operate without any errors.
  • JESD204C Transmitter IP
    • Compliant with JESD204 specification JESD204A, JESD204B.01 and JESD204C.
    • Full JESD204C transmit functionality.
    • Supports data rate upto 32 Gbps.
    • Supports programmable clock frequency up to 32 GHz.
  • JESD204C Receiver IP
    • Compliant with JESD204 specification JESD204A, JESD204B.01 and JESD204C.
    • Full JESD204C receive functionality.
    • Supports data rate upto 32 Gbps.
    • Supports programmable clock frequency up to 32 GHz.
  • O-RAN Fronthaul Transport Subsystem
    • Reliable
    • Flexible
    • Silicon Agnostic
    Block Diagram -- O-RAN Fronthaul Transport Subsystem
  • 112G PHY G2, TSMC N5 x4, North/South (vertical) poly orientation
    • Supports 1.25 to 112 Gbps data-rate
    • Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA, and OIF CEI LR/MR/VSR Electrical Interfaces protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC) support for PCIe
    Block Diagram -- 112G PHY G2, TSMC N5 x4, North/South (vertical) poly orientation
  • 112G LRM PHY STD, TSMC N4P x4, North/South (vertical) poly orientation
    • Supports 1.25 to 112 Gbps data-rate
    • Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA, and OIF CEI LR/MR/VSR Electrical Interfaces protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC) support for PCIe
    Block Diagram -- 112G LRM PHY STD, TSMC N4P x4, North/South (vertical) poly orientation
  • 112G VSR PHY, TSMC N3P x2, North/South (vertical) poly orientation
    • Supports 1.25 to 112 Gbps data-rate
    • Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA, and OIF CEI LR/MR/VSR Electrical Interfaces protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC) support for PCIe
    Block Diagram -- 112G VSR PHY, TSMC N3P x2, North/South (vertical) poly orientation
  • 112G PHY, TSMC N3P x4 1.2V, North/South (vertical) poly orientation
    • Supports 1.25 to 112 Gbps data-rate
    • Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA, and OIF CEI LR/MR/VSR Electrical Interfaces protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC) support for PCIe
    Block Diagram -- 112G PHY, TSMC N3P x4 1.2V, North/South (vertical) poly orientation
  • 112G LRM PHY, TSMC N3P x4, North/South (vertical) poly orientation
    • Supports 1.25 to 112 Gbps data-rate
    • Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA, and OIF CEI LR/MR/VSR Electrical Interfaces protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC) support for PCIe
    Block Diagram -- 112G LRM PHY, TSMC N3P x4, North/South (vertical) poly orientation
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