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Interconnect IP

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Search (723)
Compare 723 IP from 76 vendors (1 - 10)
  • SPI Slave IP transfers to/from a AMBA APB, AXI, or AHB Interconnect
    • The DB-SPI-S-AMBA-BRIDGE is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting only Slave SPI Bus transfers (both Full Duplex and Half Duplex) to/from a AMBA APB, AXI, or AHB Interconnect.
    • The DB-SPI-S-AMBA-BRIDGE contains dual clock Transmit/Receive FIFOs and Finite State Machine control to process incoming SPI transmit/receive transactions, and a AMBA Master Interface (i.e. APB, AXI, AHB5) to read or write the SPI payload data with respect to the AMBA Interconnect. No processor is required for configuration or control; the DB-SPI-S-AMBA-BRIDGE operates autonomously from reset.
    Block Diagram -- SPI Slave IP transfers to/from a AMBA APB, AXI, or AHB Interconnect
  • AMBA AXI5-Lite Interconnect Verification IP
    • Compliant with the latest ARM AXI5-Lite Protocol Specification.
    • Supports AXI5-Lite Master, Slave, Interconnect, Monitor and Checker.
    • Supports all AXI5-Lite data and address widths.
    • Supports all protocol transfer types, burst types, burst lengths, burst sizes and response types.
    Block Diagram -- AMBA AXI5-Lite Interconnect Verification IP
  • AMBA AXI5 Interconnect Verification IP
    • Compliant with the latest ARM AMBA AXI5 Protocol Specification.
    • Supports AXI5 Master, Slave, Interconnect, Monitor and Checker.
    • Supports all ARM AMBA AXI5 data and address widths.
    • Supports all protocol transfer types, burst types, burst lengths, burst sizes and response types.
    Block Diagram -- AMBA AXI5 Interconnect Verification IP
  • AMBA AXI4-Stream Interconnect Verification IP
    • Compliant with the latest ARM AMBA AXI4-Stream Protocol Specification.
    • Supports AXI4-Stream Master, Slave, Interconnect, Monitor and Checker.
    • Supports all ARM AMBA AXI4-Stream data widths.
    • Support for all Data streams including Byte stream, Continuous aligned stream, Continuous unaligned stream and Sparse stream.
    Block Diagram -- AMBA AXI4-Stream Interconnect Verification IP
  • AMBA AXI4-Lite Interconnect Verification IP
    • Compliant with the latest ARM AMBA AXI4-Lite Protocol Specification.
    • Supports AXI4-Lite Master, Slave, Interconnect, Monitor and Checker.
    • Supports all ARM AMBA AXI4-Lite data and address widths.
    • Supports all protocol transfer types and response types.
    Block Diagram -- AMBA AXI4-Lite Interconnect Verification IP
  • AMBA AXI4 Interconnect Verification IP
    • Compliant with the latest ARM AMBA AXI4 Protocol Specification.
    • Supports AXI4 Master, Slave, Interconnect, Monitor and Checker.
    • Supports all ARM AMBA AXI4 data and address widths.
    • Supports all protocol transfer types, burst types, burst lengths, burst sizes and response types.
    Block Diagram -- AMBA AXI4 Interconnect Verification IP
  • AMBA AXI3 Interconnect Verification IP
    • Compliant with the latest ARM AMBA AXI3 Protocol Specification.
    • Supports AXI3 Master, Slave, Interconnect, Monitor and Checker.
    • Supports all AXI3 data and address widths.
    • Supports all protocol transfer types, burst types, burst lengths, burst sizes and response types.
    Block Diagram -- AMBA AXI3 Interconnect Verification IP
  • AHB Multilayer Interconnect IIP
    • Compliant with AMBA AHB specification
    • Supports configurable number of AHB Master
    • Supports configurable number of AHB Slave
    • Supports standardized user interface signals for easy integration with any IP
    Block Diagram -- AHB Multilayer Interconnect IIP
  • Universal Chiplet Interconnect Express (UCIe™) PHY
    • Supports up to 32Gbps per pin including 4/8/12/16/24Gbps
    • Forwarded clock, track, and valid pins
    • Sideband messaging for link training and parameter exchange
    • KGD (Known Good Die) testing capability
    • Redundant lane repair (advanced)
    • Width degradation (standard)
    • Lane reversal
    Block Diagram -- Universal Chiplet Interconnect Express (UCIe™) PHY
  • Die-to-Die, High Bandwidth Interconnect PHY Ported to TSMC N7 X24
    • Delivers up to 4Gbps per pin with up to bidirectional 2 Tbps/mm of die edge
    • High-bandwidth, low-power, low-latency multi-channel PHY in applications requiring connections between dies within a package
    • Compliant with Intel Advanced Interface Bus (AIB) v1.1 standard
    • Compliant with IEEE 1149.1 (JTAG), 1149.6 (AC JTAG) for easy integration with SoC testability framework
    Block Diagram -- Die-to-Die, High Bandwidth Interconnect PHY Ported to TSMC N7 X24
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