IP Catalog > Peripheral IP > AMBA AHB / APB/ AXI IP > AMBA AHB / APB IP > AMBA AXI4-Stream Interconnect Verification IP

AMBA AXI4-Stream Interconnect Verification IP

Overview

AMBA AXI4-Stream Interconnect Verification IP provides an smart way to verify the ARM AMBA AXI4-Stream component of a SOC or a ASIC. The SmartDV's AMBA AXI4-Stream Interconnect Verification IP is fully compliant with standard AMBA AXI4-Stream Specification.

AMBA AXI4-Stream Interconnect Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AMBA AXI4-Stream Interconnect Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Compliant with the latest ARM AMBA AXI4-Stream Protocol Specification.
  • Supports AXI4-Stream Master, Slave, Interconnect, Monitor and Checker.
  • Supports all ARM AMBA AXI4-Stream data widths.
  • Support for all Data streams including Byte stream, Continuous aligned stream, Continuous unaligned stream and Sparse stream.
  • Support for single byte, packet and frame transfers.
  • Transfer interleaving support.
  • Support for upsizing, downsizing and merging.
  • Supports constrained randomization of protocol attributes.
  • Slave and Interconnect support fine grain control of response.
  • Programmable wait states or delay insertion. Interconnect has the ability to replicate Master/Slave inserted delays.
  • Ability to inject errors during transfer.
  • Ability to configure the width of all signals.
  • Support for bus inactivity detection and timeout.
  • Programmable Timeout insertion.
  • Supports FIFO memory.
  • Rich set of configuration parameters to control AXI4-Stream functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in coverage analysis.
  • Callbacks in Master, Slave, Interconnect and Monitor for various events.
  • Status counters for various events on bus.
  • AXI4-Stream Interconnect Verification IP comes with complete testsuite to test every feature of ARM AMBA AXI4-Stream specification.

Benefits

  • Faster testbench development and more complete verification of AMBA AXI4-Stream designs.
  • Easy to use command interface simplifies testbench control and configuration of Master, Slave and Interconnect.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

AMBA AXI4-Stream Interconnect Verification IP Block Diagram

Deliverables

  • Complete regression suite containing all the AMBA AXI4-Stream testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

Request Info

Related IPs

×
Semiconductor IP