I2C IP

• This I/O Library, developed on GlobalFoundries 55nm CMOS, delivers a complete suite of digital and analog I/O solutions with robust 2 kV HBM / 500 V CDM ESD protection and latch-up immunity.
• The library includes 1.8/3.3 V GPIOs supporting GMII and LVCMOS standards, I2C-compliant ODIOs, and flexible analog I/Os (ANA/DANA) with integrated ESD.

• I2C (Inter-Integrated Circuit) bus Interface serves as an interface between the microcontroller and the serial I2C bus.
• It provides multimaster capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing.
• It supports the standard mode (Sm, up to 100 kHz), Fast mode (Fm, up to 400 kHz), Fast mode plus mode (Fm+, up to 1MHz) and High-speed mode (Hs-mode, up to 3.4MHz).

• The I2C (Inter - Integrated Circuit) protocol is a widely used serial communication protocol for transferring data between electronic devices. It was developed by Philips in the 1980s and is now owned by NXP Semiconductors. I2C uses two bidirectional data lines called SDA (Serial Data) and SCL (Serial Clock) for communication between devices.
• It allows multiple devices to be connected to the same bus, and each device can be identified by a unique address. The protocol supports data transfer rates ranging from a few kilobits per second to several hundred kilobits per second.

• The I2C Interface provides full support for the two-wire I2C synchronous serial interface, compatible with the ACCESS.
• Bus physical layer, with additional support for the SMBus protocol, including Packet Error Checking (PEC).
• Through its I2C compatibility, it provides a simple interface to a wide range of low-cost memories and I/O devices, including: EEPROMs, SRAMs, timers, A/D converters, D/A converters, clock chips, and peripheral drivers.

• I2C (Inter-Integrated Circuit) is a low-speed communication protocol designed for embedded systems. As a Verification IP (VIP), it simulates and validates I2C interfaces, ensuring accurate data transmission, addressing, and error handling.
• This VIP supports various device roles, data rates, and stress-testing scenarios, such as clock stretching and multi-master configurations, ensuring reliable communication in applications like sensor interfacing and memory device validation

• Multiple Agents
• Multi-controllers and any number of targets
• Arbitration
• Controller arbitration is supported

• The I2CSPI-CTRL is a compact and versatile serial interface controller supporting both SPI (Serial Peripheral Interface) and I2C (Inter-Integrated Circuit) protocols.
• Its low silicon resource requirement makes it suitable for area-constrained and low-power applications, while its software compatibility with Microchip’s MSSP peripheral eases use and software integration.

• The DB-I2C-S-AHB Controller IP Core interfaces a NIOS II, ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via the Avalon System Interconnect Fabric to an I2C Bus.
• The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices.

The DB-I2C-S-AVLN is a Slave I2C Controller that controls the Transmit or Receive of data to or from external Master I2C devices. Figure 1 depicts the system view of the DB I2C-S-AVLN Controller IP Core embedded within an integrated circuit device.

• The DB-I2C-M-AVLN Controller IP Core interfaces a microprocessor via the Avalon Bus to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.
• The DB-I2C-M-AVLN is a Master I2C Controller that controls the Transmit or Receive of data to or from slave I2C devices. In an Altera FPGA, typically, the microprocessor is a NIOS II processor, but can be any FPGA embedded processor. Figure 1 depicts the system view of the DB-I2C-M-AVLN Controller IP Core embedded within an FPGA integrated circuit device.

• The DB-I2C-MS-AVLN Controller IP Core interfaces a microprocessor via the Avalon Bus to an I2C Bus in Standard-Mode (100 Kbit/s) / Fast-Mode (400 Kbit/s) / Fast-Mode Plus (1 Mbit/s) / Hs-Mode (3.4+ Mb/s) / Ultra Fast-Mode (5 mbit/s).
• The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.
• The DB-I2C-MS-AVLN is a Master / Slave I2C Controller that in Master Mode controls the Transmit or Receive of data to or from slave I2C devices while in Slave Mode allows an external I2C Master device to control the Transmit or Receive of data.