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High-Speed SerDes IP

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Compare 117 IP from 24 vendors (1 - 10)
  • 64G High-speed SerDes
    • The 64G SerDes PHY is a highly configurable PHY capable of supporting speeds up to 64Gbps within a single lane
    • The PHY has been configured to support 64G PAM-4 and NRZ specifically, but the PHY itself can be configured to support a wide range of HS SerDes protocols through changes to the PCS layer and register settings
    Block Diagram -- 64G High-speed SerDes
  • 28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process
  • High-Speed LVDS (SERDES) Transceiver
    • The LVDS_SERDES IP Core is a high-speed LVDS transmitter / receiver pair suitable for a wide range of serial interface applications.
    • The design is comprised of an independent transmitter and receiver that may be used separately or together as a single transceiver.
    Block Diagram -- High-Speed LVDS (SERDES) Transceiver
  • Ultra-Low Latency 32Gbps SerDes IP in TSMC 12nm FFC
    • Modular architecture supporting x1 to x16 lanes with a single CMU
    • Lane-based PLL architecture supporting flexible, independent data rates from 1.25 to 32Gbps
    • Ultra-low latency 2/4/8-bit parallel interface mode for lowest possible latency
    Block Diagram -- Ultra-Low Latency 32Gbps SerDes IP in TSMC 12nm FFC
  • Ultra-Low Latency 32Gbps SerDes IP in TSMC 22nm ULP
    • Modular architecture supporting x1 to x16 lanes with a single CMU
    • Lane-based PLL architecture supporting flexible, independent data rates from 1.25 to 32Gbps
    • Ultra-low latency 2/4/8-bit parallel interface mode for lowest possible latency
    Block Diagram -- Ultra-Low Latency 32Gbps SerDes IP in TSMC 22nm ULP
  • 32Gbps SerDes IP in TSMC 12nm FFC
    • Modular architecture supporting x1 to x16 lanes with a single CMU
    • Lane-based PLL architecture supporting flexible, independent data rates from 1.25 to 32Gbps
    • Configurable low latency parallel data interface for optimal system performance
    Block Diagram -- 32Gbps SerDes IP in TSMC 12nm FFC
  • 32Gbps SerDes IP in TSMC 22nm ULP
    • Modular architecture supporting x1 to x16 lanes with a single CMU
    • Lane-based PLL architecture supporting flexible, independent data rates from 1.25 to 32Gbps
    • Configurable low latency parallel data interface for optimal system performance
    Block Diagram -- 32Gbps SerDes IP in TSMC 22nm ULP
  • 100G SerDes PAM4 PHY
    • The SERDES PHY IP delivers a high-performance, low-power solution for high-speed interfaces up to 112Gbps.
    • It supports diverse applications including AI accelerators, data centers, 5G infrastructure, and automotive SoCs.
    Block Diagram -- 100G SerDes PAM4 PHY
  • SerDes
    • High-speed SerDes with ultra-low-power consumption
    • Industry’s fastest die to die communications
    • Multiprotocol SerDes: HMC, PCIe, SATA, SAS, and USB and more
    • High lane count with multiple data rates supported
  • 16Gbps SerDes IP on TSMC 12nm
    Block Diagram -- 16Gbps SerDes IP on TSMC 12nm
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Semiconductor IP