64G High-speed SerDes

Overview

The 64G SerDes PHY is a highly configurable PHY capable of supporting speeds up to 64Gbps within a single lane. The PHY has been configured to support 64G PAM-4 and NRZ specifically, but the PHY itself can be configured to support a wide range of HS SerDes protocols through changes to the PCS layer and register settings.

The hard-macro PHY is well-architected for IEEE and OIF protocols, with ESD structure and BIST function accommodated. This IP powers high-speed interconnectivity between chips, optics, and backplanes with the built-in low-jitter LC PLL to optimize the signal integrity. The Innosilicon 64G Long Reach SerDes solution meets the functionality, power, performance and area requirements of a variety of network applications.

Key Features

Fully compliant with the following standards:
IEEE 802.3 and OIF
CEI-64G+ LR PAM-4
CEI-25G+ LR/MR NRZ
400GAUI-8 LR/MR
CEI11G-LR
64Gbps/56Gbps serial data speed, support IEEE 802.3 and OIF standards electrical specifications
Support 28-32G VSR/SR/MR/LR NRZ and 64G PAM-4
Support up to -36dB+ insertion loss @14GHz
ADC/DSP-based receiver
- Auto-adaptive Equalization
- 1-tap Decision Feedback Filter
- MM Clock Data Recovery
Reference clock: 100MHz/156.25MHz from external or through on-chip
Embedded high precision low jitter LC PLL
85-ohm differential on-chip terminated drivers and receivers with automatic impedance calibration
Multiple built-in self-test modes and test pattern generation
Near-end serial loopback for testability
Proprietary low cap ESD structures
On-chip PRBS generation and verification controlled from external terminal
Well-tuned IO and PKG model to achieve good SI and performance

Benefits

Offers leading performance, power, and area per terabit
Optional PI/SI and thermal co-design service
Full support from IP delivery to production

Block Diagram

Deliverables

Verilog Sim Behavioral simulation model for the PHY
Encrypted IO spice netlist for SI evaluation
Integration Guidelines
Test Guidelines
GDSII Layout and layer map for foundry merge
Place and Route LIB and LEF views for the AFE
LVS and DRC verification reports

Technical Specifications

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