Hipi IP

MIPI UniPro Software Stack

The MIPI Alliance was created to define and promote open standards for interfaces to mobile application processors. The UniPro (Unified Protocol) is one in a family of standard addressing the mobile market. UniPro is a high speed interface technology for interconnecting integrated circuits in mobile phones or compatible products. The targeted scenario for UniPro technology is to connect chips (such as application processor to a peripheral device) within a mobile terminal.
The Arasan UniPro software stack serves as a path for applications to transmit data over the hardware stack and also to indicate the availability of data from the remote host. The stack exports a generic set of device operation APIs (such as initialization, configuration, data transfer, callback registration for event notifications, shutdown etc.) for easy integration with client applications. It provides an easy-to-use interface to client application by managing all the nitty-gritty details of UniPro protocol in the stack itself. A layered architecture for the stack makes it possible to port, configure and expand to various platforms, OS and various target hardware devices.
The UniPro software stack implements a scheduling engine and connection specific input output queue to provide better memory utilization and to provide Quality of Service (QoS) for different requirements of the stream. Hardware does the physical bus arbitration and scheduling of packets for TC0 and TC1 traffic classes at physical level. The software does the scheduling mapping at more granular reason based on requirements of a stream.

MIPI SoundWire Slave Controller 1.2

MIPI SoundWire®Slave Controller, typically integrated into audio DSP/Codecs or directly into audio peripherals such as Microphones and Amplifiers used in smart phones, tablets and mobile PCs.
The IP when integrated provides SoundWire, a new audio interface to connect to Master typically embedded in Application Processor or Audio Codecs.

MIPI SoundWire Master Controller 1.2

Compliant with MIPI SoundWire specification version 1.2
Configurable number of Data Ports Configurable Direction – Source or Sink
Implements clock gearbox with programmable frequency divider
Implements SoundWire Bus Clock Stop and WakeUp detection

MIPI SLIMbus Software Stack

Compliant with MIPI SLIMbus® Specification version 1.01
Portability in choice of OS, processors and hardware
Easy-to-use interface for applications
Fully documented generic interface API

MIPI M-PHY® 4.1 Analog Transceiver

The M-PHY is of Type 1, which apply to UFS, LLI, and CSI-3 protocols. The Multi-gear M-PHY 4.1 consists of analog transceivers, high-speed PLL, data recovery units as well as state-machine control — all in a single GDSII.
The interface to the link protocol-specific controller (host or device) is compliant with the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.

MIPI M-PHY® 3.1 Analog Transceiver

The M-PHYs are of Type 1, which apply to UFS, LLI and CSI-3 protocols.
The Multi-gear M-PHY 3.0 consists of analog transceivers, high speed PLL, data recovery units as well as the state-machine control — all in a single GDSII.
The interface to the link protocol-specific controller (host or device) is compliant to the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.

MIPI LLI Controller

The LLI Controller connects two chips together to create a single “virtual chip”, with both chips sharing the same memory.
This is achieved by the low latency from the “companion” chip to the memory interface of the host chip.

MIPI I3C Total IP Solution

The MIPI I3CⓇ Total IP solution is a seamless integration of MIPI I3CⓇ controller, MIPI I3CⓇ PHY I/O, and MIPI I3CⓇ software stack.
The MIPI I3CⓇ Total IP solution is a simplified, backward compatible with I2C, scalable, and cost-effective interface.

MIPI HSI Software Stack

Compliant with MIPI HSI Specification version 1.0
Portability in choice of OS, processors and hardware
Easy-to-use interface for applications
Fully documented generic device operation API

MIPI DSI-2 Transmitter Controller IP Core

The MIPI Display Serial Interface (DSI-2) Transmitter (host processor interface) Controller IP provides a high-speed serial interface between an application processor and display modules using either MIPI C-PHY v1.1 or MIPI D-PHY v1.2 and v2.0.

HiPi IP