Gddr6 IP

Compare 16 IP from 5 vendors (1 - 10)

GDDR6 Memory Controller IP
- JEDEC GDDR6 standard JESD250B
- Fast frequency switching
- Flexible Configuration
GDDR6 PHY IP for 12nm
- JEDEC JESD250 compliant GDDR6 support
- X16 mode, X8 mode, and pseudo-channel mode
- Low frequency RDQS mode support
Denali Controller for GDDR6
- Compatible with GDDR6 devices compliant to JESD250a
- Supports advanced RAS features including SEC/DED ECC, error scrubbing, parity, etc.
GDDR6 PHY for Samsung
- Derived from Cadence’s silicon-proven DDR, LPDDR, and high-speed SerDes designs
- Highest data rates with detailed system guidelines
GDDR6 Memory Controller
- Supports GDDR6 SGRAM
- Supports up to 16 Gbit/s/pin GDDR6 operation
GDDR6 Memory PHY - TSMC 7nm
- JEDEC JESD250C standard compliant
- Advanced process node
- East-West and North-South orientation
- 2 channels @ 16 bits/channel
GDDR6 Memory PHY - TSMC 5nm
- JEDEC JESD250C standard compliant
- Advanced process node
- East-West and North-South orientation
GDDR6 PHY for TSMC
- Single configuration supports one GDDR6 device per channel (coplanar) or two GDDR6 devices per channel (clamshell)
- Memory controller interface uses DFI 5.0-like standard with extensions for GDDR6
- Internal and external datapath loop-back modes
- Per-bit DFE, CTLE, and FFE equalization
GDDR6 Controller IP
- Supports GDDR6 protocol standard JESD250, JESD250A and JESD250B specification with version 3.11.
- Compliant with DFI-version 4.0 or 5.0 Specification.
- Supports all the GDDR6 commands as per the specs.
- Supports up to 16 AXI ports with data width upto 512 bits.
LPDDR5X/5/4X/4 combo PHY at 12nm
- Compliant with JEDEC JESD209-5C for LPDDR5x/5/4x/4 with PHY standards
- Delivering up to 8533Mbps
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks

GDDR6 IP