GDDR6 DFI Synthesizable Transactor

Overview

Key Features

• Compliant with DFI version 4.0 or 5.0 Specifications.
• Supports GDDR6 devices compliant with JEDEC GDDR6 SGRAM Standard JESD250A and JESD250B.
• Supports GDDR6 x16 or x8 clamshell modes.
• Can be configured as a single controller driving two x16 GDDR6 channels simultaneously (x32 total) or two controllers each driving one x16 GDDR6 channel.
• Supports GDDR6 operation at up to 18Gbps.
• Supports GDDR6 error detection code (EDC).
• Supports controller retries read and write transactions after EDC error detected.
• Supports GDDR6 data bus inversion (DBI) and CA bus inversion (CABI).
• Supports Per-bank and All-bank refresh.
• Supports Write Single Mask (WSM) and Write Double Mask (WDM).
• Supports GDDR6 low power modes (self-refresh and power-down).
• Support for GDDR6 device densities from 8 to 32Gb.
• Supports automatic generation and user-controlled initialization sequences.
• Supports read and write commands with or without auto-precharge.
• Supports DRAM Clock disabling feature.
• Supports Low power control features.
• Supports Error signaling.
• Supports CA Training.
• Supports WCK-DQ Training.
• Supports WCK2CK Leveling.
• Supports RDQS Toggle mode.
• Supports all types of timing and protocol violations detection for timing parameters.
• Protocol checker fully compliant with DFI version 4.0 or 5.0 Specifications.

Benefits

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

Block Diagram

Deliverables

• Synthesizable transactors
• Complete regression suite containing all the GDDR6 DFI testcases
• Examples showing how to connect various components, and usage of Synthesizable Transactor
• Detailed documentation of all DPI, class, task and function's used in verification env
• Documentation contains User's Guide and Release notes

Technical Specifications