IP Catalog > Embedded Vision Processor

Embedded Vision Processor IP

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  • Image signal processor to advance vision systems for IoT and embedded markets
    • Multi-sensor interface with up to 20-bit linear video input
    • Up to 8 independent camera sources of max resolution 48 Megapixels / 8K (8192 x 6144)
    Block Diagram -- Image signal processor to advance vision systems for IoT and embedded markets
  • Tensilica Vision Q7 DSP
    • Doubles Vision and AI Performance for Automotive, AR/VR, Mobile and Surveillance Markets
    Block Diagram -- Tensilica Vision Q7 DSP
  • Imaging and Computer Vision Processor
    • Superior performance
    • Low power consumption
    • Flexible and scalable
    Block Diagram -- Imaging and Computer Vision Processor
  • Intelligent Vision Processor
    • Fully programmable in high level languages
    • Scalar and Vector units to handle a mix of control and parallel code efficiently
    Block Diagram -- Intelligent Vision Processor
  • Tensilica Vision P6 DSP
    • 1024/512b Load/Store capabilities
    • 256 8-bit MAC
    • 8/16/32-bit fixed-point processing
    • Single-precision (FP32) and half-precision (FP16) floating-point processing
  • Tensilica Vision Q8 DSP
    • 2048/1024b Load/Store capabilities
    • 1024 8-bit MAC: 2X MAC capability versus Vision Q7 DSP
    • 8/16/32-bit fixed-point processing
    • Double-precision (FP64), single-precision (FP32), and half-precision (FP16) floating-point processing
  • NPU IP family for generative and classic AI with highest power efficiency, scalable and future proof
    • Support wide range of activations & weights data types, from 32-bit Floating Point down to 2-bit Binary Neural Networks (BNN)
    Block Diagram -- NPU IP family for generative and classic AI with highest power efficiency, scalable and future proof
  • ARC EV Processors are fully programmable and configurable IP cores that are optimized for embedded vision applications
    • ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
    • ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
    • Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
  • Digital Signal Processor IP
    • • High performance vector signal processing
    • and efficient control code processing
    • • 256 8-bit macs, 128 16-bit macs, or 64 32-bit macs per cycle
    • • Flexible vector permute operations
  • Digital Signal Processor IP
    • • High performance vector signal processing
    • and efficient control code processing
    • • 32 8-bit macs, 16 16-bit macs, or 8 32-bit macs per cycle
    • • Flexible vector permute operations
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