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Dolby Atmos for PCs IP

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Compare 40 IP from 4 vendors (1 - 10)
  • Dolby Digital/AC-3/MPEG Audio Decoding Core
    • The J1 is a core cell design of an application specific signal processor which performs both Dolby Digital/AC-3 and MPEG audio decompression in a single design.
    • The J1 is capable of decoding all AC-3 bitstreams with full support for bitstreams encoded with 5.1 channels and data rates of up to 640kb/s.
    • The J1 downmixing capability produces stereo output in either normal or Pro-Logic compatible modes, making it ideal for DVD and set-top applications.
    Block Diagram -- Dolby Digital/AC-3/MPEG Audio Decoding Core
  • ARC EM9D 32-bit DSP Enhanced Processor core based on the ARCv2DSP ISA with CCM and XY Memory
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM9D 32-bit DSP Enhanced Processor core based on the ARCv2DSP ISA with CCM and XY Memory
  • ARC EM11D Enhanced 32-bit processor core, ARCv2DSP ISA with Cache and XY Memory
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM11D Enhanced 32-bit processor core, ARCv2DSP ISA with Cache and XY Memory
  • ARC EM7D DSP Enhanced 32-bit processor core with caches, ARCv2DSP ISA, for low power embedded DSP ap
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM7D DSP Enhanced 32-bit processor core with caches, ARCv2DSP ISA, for low power embedded DSP ap
  • ARC EM5D Enhanced 32-bit processor core, ARCv2DSP ISA, for low power embedded DSP applications
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM5D Enhanced 32-bit processor core, ARCv2DSP ISA, for low power embedded DSP applications
  • ARC HS47Dx4 quad-core version of dual-issue HS47D ARCv2DSP ISA, with 100+ DSP instructions and I&D cache
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC HS47Dx4 quad-core version of dual-issue HS47D ARCv2DSP ISA, with 100+ DSP instructions and I&D cache
  • ARC HS47Dx2 dual-core version of dual-issue HS47D ARCv2DSP ISA, with 100+ DSP instructions and I&D cache
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC HS47Dx2 dual-core version of dual-issue HS47D ARCv2DSP ISA, with 100+ DSP instructions and I&D cache
  • ARC HS47D 32-bit, dual-issue processor core, ARCv2DSP ISA, with 100+ DSP instructions and I&D cache
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC HS47D 32-bit, dual-issue processor core, ARCv2DSP ISA, with 100+ DSP instructions and I&D cache
  • eDisplayPort v1.4 Transmitter Controller IP Core
    • Supports eDP 1.4b specification
    • Supports full eDP Transmitter functionality
    • Supports multi lanes upto 4 lanes.
    • Supports main link, Aux link and Hot plug functionality
    Block Diagram -- eDisplayPort v1.4 Transmitter Controller IP Core
  • HDMI 2.0 Tx PHY & Controller IP, Silicon Proven in ST 28FDSOI
    • HDMI version 2.0b compliant transmitter
    • Supports CEA-861F/VESA DMT up to 4K2K resolution@60fps
    • Supports 3D formats (Frame packing/Side by Side Half/Top & Bottom)
    • Wide range channel speed up to 6.0Gbps
    Block Diagram -- HDMI 2.0 Tx PHY & Controller IP, Silicon Proven in ST 28FDSOI
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Semiconductor IP