Trusurround®/SRS3-D® Audio Processor

Overview

The J5 is a digital VLSI core celldesign of an application specific signal processor that performs both Trusurround™ and SRS 3-D® audio “virtualization” processing in a single design. The 3-D processing allows users to enjoy benefits of a multi-channel sound source with only two reproduction channels. For Dolby Digital® (AC-3) sources, the J5 accepts full6- channel PCM inputs and performs the 3-D processing to produce output Left/Right signals. Similarly, for decoded ProLogic™ sources, the J5 accepts a 4-channel PCM input (L,C,R,S) and produces the same stereo output. When played through a conventional stereo sound system the user experiences “virtualized” multi-channel sound, as if the reproduction system was playing all 4 or 6 channels. In SRS 3-D mode, the J5 accepts a stereo PCM input and implements the SRS Labs 3-D algorithm to further spatialize the signal. The J5 downmixing capability produces stereo output in bypass mode. There is also a simple LR bypass mode which simply passes L/R inputs to the outputs. Of course, muting isalso selectable. The J5 audio quality meets the highest standards, allowing it to be used for the most demanding audio applications. The 24-bit PCM output yields a high level of compilance with the SRS specifications for Trusurround by minimizing quantization error. High precision is maintained internal to the J5.

Key Features

  • Implements SRS Labs Trusurround™ 3-D
  • Implements SRS Labs SRS 3D® also                                         
  • 6,4(Pro-Logic), or 2(stereo) channel PCM In
  • 20 bit stereo PCM output
  • Selectable Passive Matrix decoder                   
  • Bypass passthrough/downmix modes                      
  • High perfornamce datapath                             
  • Low cost two block architecture                     
  • Full Test mode capabilities for SRS testing
  • Pre-certified performance by SRS Labs, Inc.
  • 32kHz, 44.1kHz, and 48kHz sample rates 

Block Diagram

Trusurround®/SRS3-D®  Audio Processor Block Diagram

Technical Specifications

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Semiconductor IP