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Display Port/eDisplay Port IP

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Compare 715 IP from 66 vendors (1 - 10)
  • Display Controller – Ultra HD LCD / OLED Panels (AXI4/AXI Bus)
    • The DB9000AXI4-UHD LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Interconnect to an 4K/8K TFT LCD / OLED display panel.
    • The video image in frame buffer memory can be 8/10/12-bit 4:2:0 or 4:2:2 or 4:4:4 sampled YCrCb video or 4:4:4 RGB. For 4:2:0 and 4:2:2 YCrCb, the chroma components are re-sampled to 4:4:4 and color converted to RGB.
    Block Diagram -- Display Controller – Ultra HD LCD / OLED Panels (AXI4/AXI Bus)
  • Open LVDS Display Interface (OpenLDI) Verification IP
    • Full OpenLDI Display Source and Display Device functionality.
    • Supports OpenLDI v0.95 specification
    • Supports 8 serial data lines (A0 through A7) and two clock lines (CLK1 and CLK2) in the OpenLDI interface.
    • Supports DDC2B protocol to retrieve the EDID data structure from display.
    Block Diagram -- Open LVDS Display Interface (OpenLDI) Verification IP
  • Embedded Display Port Verification IP
    • Full Embedded Display port source device and sink device functionality.
    • Embedded Display port v1.3,1.4,1.4b and 1.5 compliant and based on display port specs 1.2/1.2a/1.3/1.4/2.0.
    • Support transmitter and receiver Mode.
    • Supports multi lanes upto 4 lanes.
    Block Diagram -- Embedded Display Port Verification IP
  • Display Port 2.0 Verification IP
    • Full Display port 2.0 source device and sink device functionality.
    • Supports backward compatibility with previous versions upto DPv1.4a
    • Supports multi lanes upto 4 lanes.
    • Supports control symbols for framing.
    Block Diagram -- Display Port 2.0 Verification IP
  • Display Port Verification IP
    • Full Display port source device and sink device functionality.
    • Display port supports version 1.0,1.1,1.2,1.2a,1.3,1.4,1.4a and 2.0 specification.
    • Supports multi lanes upto 4 lanes.
    • Supports control symbols for framing(Both Default & Enhanced framing mode).
    Block Diagram -- Display Port Verification IP
  • Display Port Synthesizable Transactor
    • Supports full Display port source device and sink device functionality
    • Supports multi lanes upto 4 lanes
    • Supports control symbols for framing(Both Default & Enhanced framing mode)
    • Supports interlaced & non-interlaced video stream
    Block Diagram -- Display Port Synthesizable Transactor
  • DISPLAY PORT TRANSMITTER IIP
    • Compliant with Display Port version 2.0 specification.
    • Supports full Display port Transmitter functionality
    • Supports multi lanes upto 4 lanes
    • Supports 10bit, 20bit, 40bit and 80bit parallel interfaces
    Block Diagram -- DISPLAY PORT TRANSMITTER IIP
  • DISPLAY PORT RECEIVER IIP
    • Compliant with Display Port version 2.0 specification.
    • Supports full Display port Receiver functionality
    • Supports multi lanes upto 4 lanes
    • Supports 10bit, 20bit, 40bit, and 80bit parallel interfaces
    Block Diagram -- DISPLAY PORT RECEIVER IIP
  • High-quality and powerful display processor
    • Support 8K@60FPS or multiple 4K@120FPS
    • All common HDR formats, including HDR10, HDR10+ and HLG
    • Security Features for Content Protections
    • Subjective and objective image quality
  • 2D GPU IP Core - Target Display Resolution: 8K
    • Xwindow (EXA)
    • Hardware Composer (HWC)
    • DirectFB
    • Pixel Rate (Pixels/Cycle): 4
    • Target Display Resolution: 8K
    • Direct 3D Tile Status and Buffer Option: yes
    • Formats Support: RGB & YUV FP16/32
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