DSC Encoder IP
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23
IP
from 11 vendors
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10)
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VESA DSC Encoder IIP
- Compliant with VESA Display Stream Compression Version 1.1, 1.2 and 1.2a.
- Full DSC Encoder functionality.
- Supports below coding schemes,
- Modified Median-Adaptive Prediction (MMAP)
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DSC Encoder
- Compliant with the VESA DSC 1.2a standards
- Perform encoding
- Support MMAP, BP, MPP and ICH
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VESA DSC Encoder
- VESA Display Stream Compression (DSC) 1.2b compliant
- Supports all DSC 1.2b mandatory encoding mechanisms: MMAP, BP, MPP, and ICH
- Output buffering compatible with transport stream over video interfaces
- Configurable maximum display resolution
- Configurable compressed bit rate, in increments of 1/16 bpp
- 8, 10, 12, 14, and 16 bits per video component
- YCbCr and RGB video input format
- 4:4:4, 4:2:2, and 4:2:0 native coding
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VESA DSC V1.2 Encoder
- VESA introduced the first Display Stream Compression (DSC) standard in 2014. The DSC 1.1 has been incorporated into the VESA Embedded DisplayPort (eDP) and MIPI® DSI embedded mobile interface standards. The latest VESA Display Compression-M (VDC-M) standard has also been adopted into the MIPI DSI standard. For mobile applications, DSC 1.1 and VDC-M mainly serve to reduce the video interface data rate, which reduces system power, prolongs battery life, and reduces interconnects to enable sleeker designs. For external display interfaces, DSC 1.2b extends resolution across existing connectors and cables, enabling 8K video and legacy support from the same connection.
- Being compliant with the VESA DSC 1.2a and 1.2b standards, the IP core supports various prediction schemes (MMAP, BP, MPP, ICH) as well as color formats in YCbCr and RGB. It transfers more pixel data over display links to save memory size in embedded frame buffers in display driver ICs and performs visually lossless compression, low gate count and latency for ultra-high-definition display applications. It can be easily integrated into ASIC and FPGA applications.
- Programmable display resolutions
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VESA DSC V1.2 Encoder
- Being compliant with the VESA DSC 1.2a and 1.2b standards, the IP core supports various prediction schemes (MMAP, BP, MPP, ICH) as well as color formats in YCbCr and RGB.
- It transfers more pixel data over display links to save memory size in embedded frame buffers in display driver ICs and performs visually lossless compression, low gate count and latency for ultra-high-definition display applications. It can be easily integrated into ASIC and FPGA applications.
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VESA DSC 1.2a Encoder
- Compliant with the VESA DSC 1.2a and 1.1 specifications
- Supports all DSC video formats: RGB, YCbCr, native 4:2:2/4:2:0, simple 4:2:2
- Supports the latest interface standards: HDMI 2.1, MIPI DSI, DisplayPort
- Configurable IP delivers low-power and small area
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AC VESA DSC 1.2a Encoder
- Compliant with the VESA DSC 1.2a and 1.1 specifications
- Supports all DSC video formats: RGB, YCbCr, native 4:2:2/4:2:0, simple 4:2:2
- Supports the latest interface standards: HDMI 2.1, MIPI DSI, DisplayPort
- Configurable IP delivers low-power and small area
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DSC 1.2b Encoder
- Compliant with the VESA DSC 1.2b
- Backward compatible with the VESA DSC 1.1
- Supports all DSC 1.2b mandatory and optional coding schemes
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Scalable Ultra-High Throughput VESA DSC 1.2b Encoder
- The UHT-DSC-E core is an advanced video encoder IP, compliant to the VESA Display Stream Compression (DSC) v1.2b standard.
- It supports encoding of 4:4:4, 4:2:2 and 4:2:0 video streams, in 8 to 16 bits sample depths.
- The core is scalable and has been designed for enabling ultra-high throughput video encoding, even in medium-range target implementation technologies.
