DPA IP
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66
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Programmable Root of Trust With DPA and FIA for US Defense
- Custom-designed 32-bit secure RISC-V processor
- Multi-layered security model protects all core components against a wide range of attacks
- Security model includes hierarchical privilege model, secure key management policy, hardware-enforced isolation/access control/protection, error management policy
- State-of-the-art DPA resistance, FIA protection and anti-tamper techniques
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Fast Public Key Engine with DPA or with DPA and FIA
- The SCA-resistant PKE-IP-85 family of Public Key Engine cores provide semiconductor manufacturers with superior public key cryptography acceleration.
- The cores are easily integrated into ASIC/SoC and FPGA devices, offer a high-level of resistance to Differential Power Analysis (DPA), and, optionally, offer detection of Fault Injection Attacks (FIA).
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Fast Quantum Safe Engine for ML-KEM (CRYSTALS-Kyber) and ML-DSA (CRYSTALS-Dilithium) with DPA
- Compliant with FIPS 203 ML-KEM and FIPS 204 ML-DSA standards
- Uses CRYSTALS-Kyber, CRYSTALS-Dilithium quantum-resistant algorithms
- Includes SHA-3, SHAKE-128 and SHAKE-256 acceleration
- The embedded QSE CPU combined with Rambus-supplied firmware implements the full FIPS 203/204 protocols
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DPA and FIA-Resistant Ultra-Compact FortiCrypt AES IP core
- Ultra-compact
- Ultra-efficient in terms of performance per gate
- Passes the rigorous Test Vector Leakage Assessment (TVLA) test at 1B traces
- Protected against fault injection attacks, including SIFA
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Programmable Root of Trust Family With DPA & Quantum Safe Cryptography
- Hardware Root of Trust employing a custom 32-bit RISC-V processor
- Multi-layered security model provides protection of all components in the core
- NIST CAVP and CMVP compliant for FIPS 140-3 validation
- State-of-the-art anti tamper techniques
- DPA-resistant cryptographic accelerators
- Caliptra Root of Trust for Measurement with DICE and X.509 support
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Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
- One input word per clock without any backpressure
- Design can switch stream, algorithm, mode, key and/or direction every clock cycle
- GCM: throughput is solely determined by the data width, data alignment and clock frequency
- XTS: block processing rate may be limited by the number of configured tweak encryption & CTS cores; a configuration allowing 1 block/clock is available
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ChaCha20 DPA Resistant Crypto Accelerator
- Quicken time-to-market using precertified DPA Countermeasures
- Highly secure cryptographic engine primitives
- Extensive validation using the Test Vector Leakage Assessment (TVLA) methodology (revealing no leakage beyond 100 million traces)
- Cores protected against univariate first- and second-order side-channel attacks beyond 1 billion operations
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AES Authenticated Encryption Accelerator with DPA or with DPA and FIA
- The SCA-resistant AES-IP-3X family of crypto accelerator cores provide semiconductor manufacturers with superior AES cipher acceleration.
- The cores are easily integrated into ASIC/SoC and FPGA devices and offer a high-level of resistance to various Side Channel Attacks like Differential Power Analysis (DPA), and optionally offer detection of Fault Injection Attacks (FIA).
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Security Gasket to hide transaction to range of addresses for SPA and DPA and secure Data using End-to-End ECC.
- 1. AMBA-AXI-4.0 Master and Slave
- 2. Blocks user to snoop the meaningful data.
- 3. Block User from SPA/ DPA Gassing the secure data.
- 4. End to End ECC Secured transactions.
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Security Gasket to hide transaction to range of addresses for SPA and DPA and secure Data using End-to-End ECC.
- 1. AMBA-AHB Master and Slave
- 2. Blocks user to snoop the meaningful data.
- 3. Block User from SPA/ DPA Gassing the secure data.
- 4. End to End ECC Secured transactions.
