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DDR PHY IP

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Search (434)
Compare 434 IP from 41 vendors (1 - 10)
  • Denali High-Speed DDR PHY for SMIC
    • LPDDR4X/LPDDR4/LPDDR3/DDR4/DDR3/DDR3L training with write-leveling and data-eye training
    • Optional clock gating available for low-power control
    • Memory controller interface complies with DFI standards 4.0 or 3.1
    • Internal and external datapath loopback modes
  • DDR PHY
    • DDR5/4/3 training with write-leveling and data-eye training
    • Optional clock gating available for low-power control
    • Internal and external datapath loop-back modes
    • I/O pads with impedance calibration logic and data retention capability
    • Programmable per-bit (PVT compensated) deskew on read and write datapaths
    • RX and TX equalization for heavily loaded systems
    Block Diagram -- DDR PHY
  • Denali DDR PHY for TSMC
    • Low Latency
    • Low Power and Area
    • Reliable
  • DDR PHY
    • Dolphin's hardened DDR4/3/2 SDRAM PHY and LPDDR5/4x/4/3/2 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 4266 Mbps.
    • It is fully compliant with the DFI 4.0 specification, and features include slew rate control, per-bit de-skew, gate training, read and write leveling and built-in self test (BIST).
    • In addition, our PHY IP is optimized to provide a complete solution when combined with Dolphin's DDRx and LPDDRx SDRAM Memory Controller IP.
  • DDR PHY & DDR Controller IP
    • DDR4/DDR3/DDR2 PHY IP fully compliant with the DFI 4.0 Specification.
    • LPDDR5/LPDDR4/LPDDR3/LPDDR2 PHY IP fully compliant with the DFI 4.0 Specification.
    • Support speeds up to 4266Mbps.
    • IP is split into 2 hard macros.
  • Denali High-Speed DDR PHY for TSMC 22ULP
    • LPDDR4/LPDDR3/DDR4/DDR3/DDR3L training with write-leveling and data-eye training
    • I/O pads with impedance calibration logic and data retention capability
    • Optional clock gating available for low-power control
    • Multiple PLLs for maximum system margin
  • Denali High-Speed DDR PHY for UMC
    • LPDDR4/LPDDR3/DDR4/DDR3/DDR3L training with write-leveling and data-eye training
    • I/O pads with impedance calibration logic and data retention capability
    • Optional clock gating available for low-power control
    • Multiple PLLs for maximum system margin
  • DDR multi PHY
    • Compatible with JEDEC standard DDR2/DDR3/LPDDR (or Mobile DDR)/ /LPDDR2/LPDDR3 SDRAMs
    • Operating range of 100MHz (200Mb/s) to 533MHz(1066Mb/s) in DDR2/DDR3/LPDDR2/LPDDR3 modes
    • Operating range of DC to 200MHz in Mobile DDR mode
    • PHY Utility Block (PUBL) component
  • DDR and LPDDR Combo PHY
    • Supports multiple combinations of DDR/LPDDR interfaces
    • Compliant with JEDEC DDR and LPDDR standards
    • Supports all auto calibrations
    • Industry leading area and power
  • SDRAM DDR Controller
    • Dolphin Technology offers high performance DDR4/3/2 SDRAM and LPDDR5/4x/4/3/2 SDRAM Memory Controller IP across a broad range of process technologies.
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