Denali High-Speed DDR PHY for TSMC 22ULP

Lowest latency and highest data rates for data-intensive applications

Developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms, the DDR PHY IP is silicon-proven and can provide customers with ease of integration and faster time to market. The DDR PHY IP is engineered to quickly and easily integrate into any system-on-chip (SoC), and is verified with the Denali DDR controller IP as part of a complete memory subsystem solution. The DDR PHY IP is designed to connect seamlessly and work with a thirdparty DFI-compliant memory controller. The DDR PHY IP is developed and validated to reduce the risk for the customer so that their SoC can be first time right. Developed for and available early in the lifecycle of the most advanced semiconductor process nodes, the DDR PHY IP is designed to be robust under varying noise conditions and to have interoperability with various supplier memory chips. The DDR PHY IP is part of the comprehensive Cadence Design IP portfolio comprised of an interface, Denali memory interface, analog; and systems and peripherals IP.

• LPDDR4/LPDDR3/DDR4/DDR3/DDR3L training with write-leveling and data-eye training
• I/O pads with impedance calibration logic and data retention capability
• Optional clock gating available for low-power control
• Multiple PLLs for maximum system margin
• Memory controller interface complies with DFI standards 4.0 or 3.1
• Programmable clock delay (PVT compensated) on read and write datapaths for DQS alignment
• Internal and external datapath loopback modes
• Per-bit deskew on read and write datapath

• Communications,
• Consumer Electronics,
• Data Processing,
• Industrial and Medical,
• Military/Civil Aerospace

• GDS II macros with abstract in LEF
• Verilog post-layout netlist
• STA scripts for use at chip or standalone PHY levels
• Liberty timing model
• SDF for back-annotated timing verification