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Search (3,442)
Compare 3,442 IP from 198 vendors (1 - 10)
  • HBM4 Controller IP
    • Supports JEDEC standard HB4 DRAM
    • DFI 5.1 compliant interface to HBM4 PHY
    • Multiport Arm® AMBA® interface (AXI™) with managed QoS per pseudo-channel or single-port host interface(HIF), per channel 
    • Data rate support 12 Gbps or higher
  • Microsecond Channel (MSC/MSC-Plus) Controller
    • The MSC-CTRL IP core implements a high-speed serial interface controller designed to connect a microcontroller or SoC to external power devices or sensors.
    • It implements the Microsecond Channel (MSC) and Microsecond Channel Plus (MSC-Plus) protocols—derived from the Microsecond Bus (uSB) serial concept—and acts as a bus master for downstream transmission and as a bus slave for upstream transmission.
    Block Diagram -- Microsecond Channel (MSC/MSC-Plus) Controller
  • CAN-FD Controller
    • The Controller Area Network (CAN) is a highly reliable serial bus protocol defined in the Bosch CAN specifications for standard CAN 2.0B and CAN FD, as well as ISO 11898-1:2024.
    • The TES CAN Flexible Data-Rate Controller IP core is a Hardware IP core written in VHDL.
    Block Diagram -- CAN-FD Controller
  • LPDDR6/5X/5 Controller IP
    • Supports JEDEC standard LPDDR6, LPDDR5X and LPDDR5 SDRAMs
    • Support for data rates up to 14.4 Gbps for LPDDR6, 10.67 Gbps for LPDDR5X, and 6.4 Gbps for LPDDR5
    • Multiport Arm® AMBA® interface AXI™4 with managed QoS or single-port host interface to the DDR controller
    • DFI 5.2 compliant interface to Synopsys LPDDR6/5X/5 PHY
    Block Diagram -- LPDDR6/5X/5 Controller IP
  • PCIe PHY and controller solution
    • Brite 16Gbps PCIe PHY and controller solution provide high efficient interconnection that is optimized for PPA performance. The System can support short-reach or long-reach channels for plenty application scenarios.
    • Brite PCIe controller to AXI architecture provides a high-performance, easy-to-use interconnect solution between PCI Express and the latest version of the AXI protocol. It inherits the leading architecture and features an AXI user interface with built-in DMA, compliant with the AMBA® AXI3 and AXI4 specifications.
    Block Diagram -- PCIe PHY and controller solution
  • Fault Tolerant DDR2/DDR3/DDR4 Memory controller
    • FTADDR is a memory controller for DDR2,DDR3 and DDR4 SDRAM memory devices.
    • It uses a strong error correction code to achieve exceptional fault tolerance
    Block Diagram -- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
  • PCIe Controller
    • Dolphin PCIe Controller is a high-performance and compact solution for PCIe provide high-throughput, low-latency, and power-efficient external connectivity in SoCs for mobile, networking, storage, cloud computing, and automotive applications.
    • The PCIe Controller consists of silicon-proven digital controllers, PHYs and verification IP, all of which are designed to support all required features of the PCIe 5.0 32GT/s (Gen5), PCIe 4.0 16GT/s (Gen4), 3.1 8GT/s (Gen3), 2.1 5GT/s (Gen2) and 1.1 2.5GT/s (Gen1).
  • SDRAM DDR Controller
    • Dolphin Technology offers high performance DDR4/3/2 SDRAM and LPDDR5/4x/4/3/2 SDRAM Memory Controller IP across a broad range of process technologies.
  • MIPI RX controller on SMIC 28nm
    • MIPI RX controller is a mass production IP in SMIC 28nm supported MIPI DSI & DCS protocols.
  • DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm
    • The DDR5&DDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device
    • The TX is designed to send information from PHY to DRAM and RX is designed to receive information which is from DRAM._x000D_ It supports DDR5&DDR4 interface
    • The DDR5 DQ data rate can be up to 4800Mb/s, and the DDR4 DQ data rate can be up to 3200Mb/s and CA is SDR mode.
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