Cadence IP

Compare 204 IP from 16 vendors (1 - 10)

224G SerDes PHY and controller for UALink for AI systems
- UALink, the standard for AI accelerator interconnects, facilitates this scalability by providing low-latency, high-bandwidth communication.
- As a member of the UALink Consortium, Cadence offers verified UALink IP subsystems, including controllers and silicon-proven PHYs, optimized for robust performance in both short and long-reach applications and delivering industry-leading power, performance, and area (PPA).
HBM4E PHY and controller
- Advanced clocking architecture minimizes clock jitter
- DFI PHY Independent Mode for initialization and training
- IEEE 1500 interface, memory BIST feature, and loop-back function
- Supports lane repair
DDR5 MRDIMM PHY and Controller
- The DDR5 12.8Gbps MRDIMM Gen2 PHY and controller memory IP system solutions double the performance of DDR5 DRAM.
- The DDDR5 12.8Gbps design and architecture address the need for greater memory bandwidth to accommodate unprecedented AI processing demands in enterprise and data center applications, including AI in the cloud.
Simulation VIP for xSPI
- xSPI Profile 1
- SPI (Read Zero Latency), DUAL (1-1-2, 1-2-2), Quad (As per JESD251-A1), and Octal modes Data Rate: STR and DTR
- Modes
- SPI-STR (1S-1S-1S), QUAD-STR (4S-4S-4S), OCTAL-STR(8S-8S-8S), and OCTAL-DTR (8D-8D-8D) modes
Simulation VIP for UFS
- Interfaces
- DPDN I/F and RMMI I/F when used with UniPro VIP. CPort signaling pin I/F and CPort message using transactions
- UTP Layer - UPIUs
- NOP IN, NOP OUT, Query Request/ Response, Task Management Request/ Response, Command, Response, Data Out, Data In
Simulation VIP for UCIE
- Protocol Layer Features
- Streaming mode
- PCIe mode
- Protocol FDI LSMs
Simulation VIP for Toggle NAND
- Speed
- Up to 200MHz or 400Mbps per DQ pin
- Up to 600MHz or 1200Mbps per DQ pin (Version 3.0/4.0)
- Bits per Cell
Simulation VIP for TileLink
- Channels
- Drive, sample, and check the signals and operations on channels A and D for TL-UL/TL-UH conformance level and on channels A, B, C, D and E for TL-C conformance level
- TL-UL
- Support for TL-UL conformance level including Flow Control Rules, Deadlock Freedom, Request-Response message ordering, Errors and Byte lanes
Simulation VIP for SPI NAND
- Operation Modes
- Single I/O, Dual I/O, and Quad I/O (Q-SPI and QSPI) and serial mode 0 and mode 3
- Pins
- HOLD# and WP# Pins functionalities
Simulation VIP for SPI
- Full Duplex
- Simultaneous transfer from Manager and Subordinate
- Variable Size Shift Registers
- 8, 16, and 32-bit shift register for Tx and Rx