BCH Encoder Decoder IP
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9
IP
from 8 vendors
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9)
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DVB-S2 LDPC BCH Decoder and Encoder
- Irregular parity check matrix
- Layered Decoding
- Minimum sum algorithm
- Soft decision decoding
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DVB-S2X LDPC BCH Decoder and Encoder
- Improved performance
- Improved efficiency w.r.t. Shannon’s limit
- Finer gradation of code rate and SNR
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BCH encoder and decoder for NAND FLASH
- Parameter customizable
- AXI interface, easy integration
- High throughput with low complexity hardware
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DVB-S2 BCH and LDPC Encoder and Decoder
- Compliant with ETSI 302 307 V1.2.1 (2009-08) (DVB-S2).
- Support for short blocks (16200 bits) and long blocks (64800 bits).
- Support for all modulation schemes (QPSK, 8-PSK, 16-APSK, 32-APSK).
- Support for all interleaving schemes of all modulation schemes.
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BCH Intel® FPGA IP Core
- The Bose, Chaudhuri, and Hocquenghem (BCH) error correction intellectual property (IP) core is typically used in NAND flash applications
- The BCH Intel FPGA IP core is often used as a companion code with other forward error correction (FEC) IP cores, such as the Reed-Solomon and low-density parity-check (LDPC) IP cores.
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BCH Encoder/Decoder
- High-speed encoder and decoder
- Codeword length 1023 bits
- 903 information bits in the codeword
- Maximum number of error bits that can be corrected =12
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DVB-T2 Rx Bit Chain
- Short and Long Frames
- SISO
- Flexible channel BW (1.7, 5, 6, 7, 8, and 10) MHz
- Flexible modulation (QPSK, 16QAM, 64QAM, and 256QAM)
- Flexible FFT size (1, 2, 4, 8, 16, and 32) K
- Flexible guard interval (1/128, 1/32, 1/16, 19/256, 1/8, 19/128, and 1/4)