Analog / Mixed-Signal IP
Filter
Compare
80
IP
from 16 vendors
(1
-
10)
-
Specialed 20V Analog I/O in TSMC 55nm
- A TSMC 55nm LP Specialized 20V Analog I/O in Standard Low Voltage CMOS
- This silicon-proven TSMC 55nm LP 20V ESD cell is a high-voltage electrostatic discharge (ESD) protection solution specifically engineered forlow-power and high-performance applications.
- This ESD cellis designed to safeguard high- voltage interfaces commonly found in analog, mixed-signal, RF, and power management ICs, where protection against electrostatic discharge events is critical for long-term reliability.
-
Complete measurement analog front end (AFE) IP for single phase power metering
- Embedded Computation Engine for utility billing applications
- Low noise Programmable Gain Amplifier (PGA), to reach the best class accuracy with each type of sensors
- Embedded power management for the best resilience to power supply noise
-
Complete measurement analog front end (AFE) IP for single phase power metering
- Embedded Computation Engine for utility billing applications
- Low noise Programmable Gain Amplifier (PGA), to reach the best class accuracy with each type of sensors
- Embedded power management for the best resilience to power supply noise
-
Complete measurement analog front end (AFE) IP for three-phase power metering
- Embedded Computation Engine for utility biling applications
- Low noise Programmable Gain Amplifier (PGA), to reach the best class accuracy with each type of sensors
- Embedded power management for the best resilience to power supply noise
-
Complete measurement analog front end (AFE) IP for three-phase power metering
- Embedded Computation Engine for utility billing applications
- Low noise Programmable Gain Amplifier (PGA), to reach the best class accuracy with each type of sensors
- Embedded power management for the best resilience to power supply noise
-
Digital and mixed-signal IP and ASIC RISC-V reference design for USB Type-C/PD power adapter/charger
- RISC-V RV32EC processor subsystem with debug module, JTAG debug transport, and instruction and data ROM and SRAMs
-
1.8V GPIO, 1.8V & 3.3V Analog in TSMC 180nm BCD
- The silicon-proven I/O library in TSMC 180nm BCD provides a reliable and flexible solution for mixed-signal, power management, and BCD applications.
- The library includes a 1.8V digital I/O cell, optimized for up to 100MHz operation at 15pF, ensuring efficient high-speed performance.
- It also features 1.8V and 3.3V baseline analog I/Os, along with custom low-leakage 3.3V analog I/Os, tailored for low-power and precision-driven designs.
-
ISO/IEC 7816-3 Analog Front End
- five fully-integrated I/O pads: CLK, RST, I/O, VCC and GND
- fully compliant with the ISO/IEC 7816-3 standard (class A, B and C)
- proven track record through mass production in 130 nm CMOS process
- square pad with 80 µm x 80 µm opening
-
Power and Clock Generation IP - GLOBALFOUNDRIES® 22FDX®
- Tightly integrated power management platform with a soft-IP wrapper around Analog / Mixed-Signal hard macros which generate all supply voltages and clock signals needed to run highly efficient SoCs in GlobalFoundries® 22FDX®.
- Running from only one supply voltage and reference clock, the IP generates its own internal supplies and references, and those needed to run the Racyics® ABX® Generator.
-
PLL
- High Frequency Accuracy: Ensures precise frequency generation and synchronization
- Wide Frequency Range: Supports a broad range of output frequencies, catering to various applications
- Low Jitter: Provides minimal phase noise and jitter, essential for high-speed data communication and processing
- Fast Lock Time: Quickly achieves lock to the desired frequency, improving system efficiency