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Analog / Mixed-Signal IP

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Search (78)
Compare 78 IP from 16 vendors (1 - 10)
  • HBM3 PHY IP at 7nm
    • Unbeatable performance-driven and low-power-driven PPA
    • Ultra-low read/write latency with programmable PHY boundary timing
    Block Diagram -- HBM3 PHY IP at 7nm
  • GDDR6 PHY IP for 12nm
    • JEDEC JESD250 compliant GDDR6 support
    • X16 mode, X8 mode, and pseudo-channel mode
    • Low frequency RDQS mode support
    Block Diagram -- GDDR6 PHY IP for 12nm
  • 112G PHY, TSMC N7 x4, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G PHY, TSMC N7 x4, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N7 x4, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N7 x4, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N7 x2, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N7 x2, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N7 x1, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N7 x1, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N6 x2, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N6 x2, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N6 x1, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N6 x1, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N5 x4, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N5 x4, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N3P x4 1.2V, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N3P x4 1.2V, North/South (vertical) poly orientation
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